I would like to know the duty-cycle requirements for the ENET_REF_CLK input in RGMII mode. We are using the KSZ9031RNX PHY which has the following errata:
The 125MHz reference clock (CLK125_NDO pin) output
has duty cycle variation when the KSZ9031 links up in
1000Base-T Slave mode, resulting in wide variation on
the falling clock edge.
Has anyone successfully used this PHY with the i.MX6 while driving ENET_REF_CLK from CLK125_NDO output of the PHY?
One of the workarounds is to only use the rising edge of the clock provided on CLK125_NDO, but I'm unsure how exactly ENET_REF_CLK is used internally. Does it drive RGMII_TXC directly or is there a PLL in between?
There is a similar question from Clemens Gruber at the link below, but the question as to how ENET_REF_CLK is used internally and exactly what the duty cycle requirements are has not been answered. BTW, thanks Clemens Gruber for alerting me to the KSZ9031RNX errata