eMMC DDR mode

[angelo_d]

Dear all,

i am actually using a eMMC powered 3.3V as normal MMC 8 bit mode.

I have seen imx6q supports eMMC DDR mode. So i enabled (set resitors approriate),

but have no more working boot (u-boot and Linux not executed, empty tty output).

Is it enough to set the jumper on board for DDR (changed EIM_DA15 to 1),

or there is something else to setup ?

Thanks,

angelo

[igorpadykov]

Hi angelo

for emmc DDR boot one also needs to set BOOT_CFG2[2](DLL override),

with MMC_DLL_DLY[6:0] values found experimentally.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[angelo_d]

Hi Igor,

ok, DDR mode works. I finally see it active at u-boot loading and linux image loading.

I confirm your suggested settings:

BOOT_CFG2[5:7]

BOOT_CFG2[2](DLL override), with MMC_DLL_DLY[6:0] to be set experimentally.

Thanks for the great support.

Best regards

[angelo_d]

Hi Igor,

many thanks, trying, then will report here.

How should i set MMC_DLL_DLY[6:0] since they should be read from the ROM bootloader prior to load u-boot from eMMC ?

Do you know if there can be any limitation using 3.3 voltage for the eMMC with DDR mode ?

Best Regards

Angelo

[igorpadykov]

Hi Angelo

MMC_DLL_DLY[6:0] values are found experimentally,

no imitation for using 3.3 voltage.

Best regards

igor

[angelo_d]

Hi Igor,

still thanks for support.

I have DDR mode enabled, (DDR and DLL override boot_cfg bits set, so i suppose to be into DDR mode). I can boot now, MMC_DLL_DLY[6:0] are now left uset, emmc is very near to cpu and tracks quite similar, so i am expecting no delay are needed.

BTW, at 50 Mhz data transfert i don't see any evidence of DDR bit shapes. Seems i am still in SDR.

Every hint is appreciated.

[igorpadykov]

Hi Angelo

yes, waveforms are the same, check

sect.4.11.4.2 eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing  IMX6DQCEC

~igor

[angelo_d]

Hi Igor,

thanks,

what i mean is that i was expecting to see 2 data bits for a single clock cycle, as per DDR. Of course depend from the data pattern i look, anyway, i check better, but don't seems to see the data bits changing on each clock edge, as i am expecting.

I am using u-boot, is it possible i have to reconfigure usdhc4 controller for DDR mode from u-boot (i am assuming HW boot_cfg settings are enough) ?