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I.MX6 Solo/DL PCIE clock issue

Question asked by Papadopolis Umbreluta on Feb 3, 2015
Latest reply on Oct 19, 2015 by Dragan Prnjatovich

Hi All,

 

I have next problem:

 

I use WEC7 and PCIE. Quad and Dual works without problem. I use SATA clock and ANA_MISC1 register to link-up. This works perfect.

I try to migrate to Solo and DL. I didn't get very clear information about this so I contact Freescale. From Freescale I got next feedback:

- there's no difference between Solo/DL and Quad/Dual.

I get very confuse because Solo doesn't have SATA so I can't use SATA clock for PCIE. Also looks very strange that Freescale engineer are not informed that there's difference between Solo and Dual/Quad.

Also they was not able to give me some clear information how to start link-up. Just generic bla,bla...

My code looks like:

 

CLRREG32(&g_pIOMUX->GPR[1], IOMUX_GPR1_TEST_PWR_DOWN_MASK);

 

/* Enable the PCIE clock */

INSREG32BF(&g_pCCM->CBCMR, CCM_CBCMR_PCIE_AXI_CLK_SEL,0);

OALStall(200000);

 

// enable PCIE clock

INSREG32BF(&g_pPLLENET->CTRL, PLL_ENET_CTRL_ENABLE_PCIE,1);

 

nValue = INREG32(&g_pPLLENET->CTRL);

nValue &= (~(0x3<<14)); // Select the 24MHz oscillator as source

nValue |=(0x1<<20)|(0x1<<13)|(0x0<<14); // Select the 24MHz oscillator as source and 100 Mhz clk

nValue &= (~((0x1<<16) | (0x1<<12))); // BYPASS/POWERDOWN

OUTREG32(&g_pPLLENET->CTRL, nValue);

 

WaitForPLLLock();

 

// Enable pcie clock (125M_root_enable)

INSREG32(&g_pCCM->CCGR[4],CCM_CGR4_PCIE_ROOT_MASK,DDK_CLOCK_GATE_MODE_ENABLED_ALL << CCM_CGR_SHIFT(DDK_CLOCK_GATE_INDEX_PCIE_ROOT));

 

// Enable pcie phy ref clock in GPR1 reg

SETREG32(&g_pIOMUX->GPR[1], IOMUXC_GPR1_PCIE_REF_CLK_EN)

 

Can you tell me where I mistake to start clock for PCIE?

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