I have next problem:
I use WEC7 and PCIE. Quad and Dual works without problem. I use SATA clock and ANA_MISC1 register to link-up. This works perfect.
I try to migrate to Solo and DL. I didn't get very clear information about this so I contact Freescale. From Freescale I got next feedback:
- there's no difference between Solo/DL and Quad/Dual.
I get very confuse because Solo doesn't have SATA so I can't use SATA clock for PCIE. Also looks very strange that Freescale engineer are not informed that there's difference between Solo and Dual/Quad.
Also they was not able to give me some clear information how to start link-up. Just generic bla,bla...
My code looks like:
/* Enable the PCIE clock */
// enable PCIE clock
nValue = INREG32(&g_pPLLENET->CTRL);
nValue &= (~(0x3<<14)); // Select the 24MHz oscillator as source
nValue |=(0x1<<20)|(0x1<<13)|(0x0<<14); // Select the 24MHz oscillator as source and 100 Mhz clk
nValue &= (~((0x1<<16) | (0x1<<12))); // BYPASS/POWERDOWN
// Enable pcie clock (125M_root_enable)
INSREG32(&g_pCCM->CCGR,CCM_CGR4_PCIE_ROOT_MASK,DDK_CLOCK_GATE_MODE_ENABLED_ALL << CCM_CGR_SHIFT(DDK_CLOCK_GATE_INDEX_PCIE_ROOT));
// Enable pcie phy ref clock in GPR1 reg
Can you tell me where I mistake to start clock for PCIE?