I.MX6 Solo/DL PCIE clock issue

[alabama2000]

Hi All,

I have next problem:

I use WEC7 and PCIE. Quad and Dual works without problem. I use SATA clock and ANA_MISC1 register to link-up. This works perfect.

I try to migrate to Solo and DL. I didn't get very clear information about this so I contact Freescale. From Freescale I got next feedback:

- there's no difference between Solo/DL and Quad/Dual.

I get very confuse because Solo doesn't have SATA so I can't use SATA clock for PCIE. Also looks very strange that Freescale engineer are not informed that there's difference between Solo and Dual/Quad.

Also they was not able to give me some clear information how to start link-up. Just generic bla,bla...

My code looks like:

CLRREG32(&g_pIOMUX->GPR[1], IOMUX_GPR1_TEST_PWR_DOWN_MASK);

/* Enable the PCIE clock */

INSREG32BF(&g_pCCM->CBCMR, CCM_CBCMR_PCIE_AXI_CLK_SEL,0);

OALStall(200000);

// enable PCIE clock

INSREG32BF(&g_pPLLENET->CTRL, PLL_ENET_CTRL_ENABLE_PCIE,1);

nValue = INREG32(&g_pPLLENET->CTRL);

nValue &= (~(0x3<<14)); // Select the 24MHz oscillator as source

nValue |=(0x1<<20)|(0x1<<13)|(0x0<<14); // Select the 24MHz oscillator as source and 100 Mhz clk

nValue &= (~((0x1<<16) | (0x1<<12))); // BYPASS/POWERDOWN

OUTREG32(&g_pPLLENET->CTRL, nValue);

WaitForPLLLock();

// Enable pcie clock (125M_root_enable)

INSREG32(&g_pCCM->CCGR[4],CCM_CGR4_PCIE_ROOT_MASK,DDK_CLOCK_GATE_MODE_ENABLED_ALL << CCM_CGR_SHIFT(DDK_CLOCK_GATE_INDEX_PCIE_ROOT));

// Enable pcie phy ref clock in GPR1 reg

SETREG32(&g_pIOMUX->GPR[1], IOMUXC_GPR1_PCIE_REF_CLK_EN)

Can you tell me where I mistake to start clock for PCIE?

[draganprnjatovi]

Hi Papadopolis

Did you find solution for your problem

It seems that I have the same problem with Quad

Thanks

Dragan

[alabama2000]

Is it somebody in this world which can help freescale to understand how PCI clock it's working? Looks they design a processor and have no idea how to start PCI clock. Upppsss.

[igorpadykov]

Hi Papadopolis

regarding PCIe module, yes there's no difference between Solo/DL and

Quad/Dual, both use identical PCIe module.

However you are using SATA clock 100MHz as reference clock for PCIe

module, but this is non-typical option, it is not used in Freescale

BSPs. Standard option is 125MHz and this is described in

IMX6SDLRM sect.18.5.1.3.6 Ethernet PLL

Example of configuartion with 125MHz one can find in SDK PCIe

example for MCIMX6-DL SDP board i.MX 6Series Platform SDK

Best regards

igor

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[alabama2000]

Hi Igor,

Thank you very much for fast reply.

1. I understand that using SATA it's not typical option but quite used. If you google it you will find that 90% of implementation use SATA clock.

2. Please be more specific regarding example. Link what you send it to me goes to no example. Until now your explanation go to nowhere except that you copy and paste some documentation which I already know it.

3. If you look to my code you will see that I use this clock but sure it's something wrong setting clock.

4. If you know what to do please describe it. If not please don't lost my time.

BR

[igorpadykov]

Hi Papadopolis

below link to SDK, please read iMX6_Firmware_Guide.pdf

"MX6_PLATFORM_SDK "

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&nodeId=018rH3ZrDRB24A&fpsp=1&t...

~igor

[alabama2000]

Hi Igor,

Thank you very much for link. This document doesn't have nothing to do with PCIE or other info regarding this problem. I want to ask very polite to stop post replies to this issue because you are far far away from this problem . If you are freescale internal I suggest to update your CV (this is not a professional support, just a bad joke).

BR