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FlexCan RxFIFO

Question asked by Derek Krouze on Dec 16, 2014
Latest reply on Dec 23, 2015 by arnogir



I am currently trying to use the FlexCan RxFifo on a K61 using MQX 4.1.1. However I am noticing that the messages always come in on the last buffer while mqx always checks message buffer 0. So when I start the system the first 5 messages my CAN system receives are all 0's and my system is always 5 messages behind. Am I missing initializing something so they system doesn't assume that all the FIFO buffers are in use already? I see in the datasheet that "Before enabling the RFEN, the CPU must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now belonging to FIFO as having contents to be serviced" however I look at the reigsters and it appears everything is cleared correctly. Any help would be greatly appreciated.