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Relationship between jtagclk and programming speed for MC56F8323

Question asked by Jan Coufal on Sep 3, 2014
Latest reply on Sep 10, 2014 by Jan Coufal


We use MC56F8323 and we recently encountered a problem, where the flash memory changes itself on the higher temperatures ( >95°C).

Thanks to this forum we found out, that problem is caused by improper setting of FMCLKD register during initialization of our bootloader, which lead to the wrong programming speed (2Mhz)


For some reason, we cannot change the bootloader code, so we adjusted manufacturing process to not use our bootloader (with improper settings), but JTAG connector and FlashProgrammer tool (v1.2)


However, there is a question about jtagclk and its relation to the programming speed.

The 56800E Flash Programmer User Guide says about -jtagclk this:

This option tells the CCS server the frequency (kHz) to run the JTAG interface. The default value is 800kHz. Faster clock speeds allow for faster programming, but if the clock is set too fast, the DSC chip may not be able to process incoming data quickly enough, eventually leading to a programming failure.

And the 56F8300 Peripheral User Manual requires the programming speed to be between 150-200kHz:

Setting FMCLKD to a value so FCLK <150kHz can destroy the Flash due to overstress. Setting FMCLKD to a value so FCLK >200kHz can result in incomplete programming or erasure of the memory array cells.



Our questions are:

Is -jtagclk speed related to the programming speed and FMCLKD setting? And if so, then how? (1:1 ratio?)

How should we set this option to ensure that programming speed will be correct?




Jan Coufal