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J-Link and iMX6

Question asked by Erez Steinberg on Aug 25, 2014
Latest reply on Aug 25, 2014 by Erez Steinberg

Dear experts,

 

I have a custom board with a Freescale iMX6 Solo CPU, and trying to use J-Link Commander to connect to the device.

I'm getting an error message, as seen in the log below.

 

Any ideas what might be the reason for this?

 

 

/////// Log Start /////

SEGGER J-Link Commander V4.90b ('?' for help)

Compiled Aug 14 2014 09:41:15

DLL version V4.90b, compiled Aug 14 2014 09:40:57

Firmware: J-Link Ultra V4 compiled Jul 28 2014 08:28:13

Hardware: V4.00

S/N: 504301229

Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB

VTarget = 3.116V

Info: TotalIRLen = 13, IRPrint = 0x0101

 

 

WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet=2)

 

 

Info: ARM AP[0]: 0x44770001, AHB-AP

Info: ARM AP[1]: 0x24770002, APB-AP

Info: Found Cortex-A9 r2p10

Info: 6 code breakpoints, 4 data breakpoints

Info: Debug architecture ARMv7.0

Info: Data endian: little

Info: Main ID register: 0x412FC09A

Info: L1 (I-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way

Info: L1 (D-cache): 32 KB, 256 sets, LineSize 32 bytes, 4-way

Info: System control register:

Info:   Instruction endian: little

Info:   Level-1 instruction cache enabled

Info:   Level-1 data cache disabled

Info:   MMU disabled

Info:   Branch prediction disabled

Found 3 JTAG devices, Total IRLen = 13:

#0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)

#1 Id: 0x00000001

#2 Id: 0x1891B01D

Cortex-A9 identified.

Target interface speed: 100 kHz

J-Link>r

Reset delay: 0 ms

Reset type NORMAL: Toggle reset pin and halt CPU core.

Info: Cortex-A/R (reset): Re-initializing debug logic.

 

 

WARNING: CPU not halted after Reset, halting using Halt request

 

 

****** Error: Bad JTAG communication: Write to IR: Expected 0x1, got 0xF (TAP Command : 10) @ Off 0x5.

 

 

 

 

//////// End //////////

 

 

Regards,

Erez

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