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[Vybrid]  Coremark baremetal porting

Question asked by du Maugouer Brieuc on Jul 2, 2014

Hello

 

     I'm currently porting Coremark Benchmark to the vybrid VF6 to evaluate the performance of this SoC. I'm using the twr-vf65gs10 board. I first built it on Timesys linux and got a result around 835 Iterations per second, but when I run it on both Cortex-M4 or Cortex-A5 baremetal I get very low results compared to what I could expect. Does anyone knows why I'm not able to get the same level of performance when performing the baremetal version of the test ?

 

 

Here's the log of the Coremark performed on linux :

 

2K performance run parameters for coremark.

CoreMark Size    : 666

Total ticks      : 13165

Total time (secs): 13.165000

Iterations/Sec   : 835.548804

Iterations       : 11000

Compiler version : GCC4.8.2

Compiler flags   : -O2 -DPERFORMANCE_RUN=1  -lrt

Memory location  : Please put data memory location here

            (e.g. code in flash, data on heap etc)

seedcrc          : 0xe9f5

[0]crclist       : 0xe714

[0]crcmatrix     : 0x1fd7

[0]crcstate      : 0x8e3a

[0]crcfinal      : 0x33ff

Correct operation validated. See readme.txt for run and reporting rules.

CoreMark 1.0 : 835.548804 / GCC4.8.2 -O2 -DPERFORMANCE_RUN=1  -lrt / Heap

 

and some results obtained with the baremetal benchmark with different clocks and memory settings

 

***Core CA5 freq 500MHz, mem SRAM, bus 83.5MHz

 

2K performance run parameters for coremark.

CoreMark Size    : 666

Total ticks      : 9680

Total time (secs): 77

Iterations/Sec   : 129

Iterations       : 10000

Compiler version : ARMCC 5

Compiler flags   : -O3 -Otime --cpu=Cortex-A5

Memory location  : STACK

seedcrc          : 0xe9f5

[0]crclist       : 0xe714

[0]crcmatrix     : 0x1fd7

[0]crcstate      : 0x8e3a

[0]crcfinal      : 0x988c

Correct operation validated. See readme.txt for run and reporting rules.

 

 

***Core CA5 freq 396MHz, mem SRAM, bus 66MHz

2K performance run parameters for coremark.

CoreMark Size    : 666

Total ticks      : 12099

Total time (secs): 96

Iterations/Sec   : 104

Iterations       : 10000

Compiler version : ARMCC 5

Compiler flags   : -O3 -Otime --cpu=Cortex-A5

Memory location  : STACK

seedcrc          : 0xe9f5

[0]crclist       : 0xe714

[0]crcmatrix     : 0x1fd7

[0]crcstate      : 0x8e3a

[0]crcfinal      : 0x988c

Correct operation validated. See readme.txt for run and reporting rules.

 

 

***Core CA5 freq 396MHz, mem DDR , bus 66MHz

 

2K performance run parameters for coremark.

CoreMark Size    : 666

Total ticks      : 26220

Total time (secs): 209

Iterations/Sec   : 47

Iterations       : 10000

Compiler version : ARMCC 5

Compiler flags   : -O3 -Otime --cpu=Cortex-A5

Memory location  : STACK

seedcrc          : 0xe9f5

[0]crclist       : 0xe714

[0]crcmatrix     : 0x1fd7

[0]crcstate      : 0x8e3a

[0]crcfinal      : 0x988c

Correct operation validated. See readme.txt for run and reporting rules.

 

 

 

***Core CA5 freq 500MHz, mem DDR, bus 83.5MHz

 

2K performance run parameters for coremark.

CoreMark Size    : 666

Total ticks      : 23673

Total time (secs): 189

Iterations/Sec   : 52

Iterations       : 10000

Compiler version : ARMCC 5

Compiler flags   : -O3 -Otime --cpu=Cortex-A5

Memory location  : STACK

seedcrc          : 0xe9f5

[0]crclist       : 0xe714

[0]crcmatrix     : 0x1fd7

[0]crcstate      : 0x8e3a

[0]crcfinal      : 0x988c

Correct operation validated. See readme.txt for run and reporting rules.

 

 

You'll find attached to this post my workspace

 

Thank you for your help

 

Brieuc

Original Attachment has been moved to: workspace.zip

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