mx6q reboot problem

[mrleo]

In arch/arm/kernel/process.c, arm_machine_restart () function,

Void arm_machine_restart (char mode, const char *cmd)

{

/ * Flush the console to make sure all the relevant messages make it

* out to the console drivers

Arm_machine_flush_console ();

/ * Disable interrupts first * /

Local_irq_disable ();

Local_fiq_disable ();

/ *

* Tell the MM system that we are going to reboot

* we may need it to insert some 1:1 mappings so that

* soft boot works

*

Setup_mm_for_reboot (mode);

/ * Clean and * / invalidate caches

Flush_cache_all ();

/ * Turn off caching * /

Cpu_proc_fin ();

/ * Push out any further dirty data, and ensure cache is empty

Flush_cache_all ();

/ *

* Now call the architecture specific reboot code

*

Arch_reset (mode, CMD);

/ *

* Whoops the architecture was unable to reboot

* Tell the user!

*

Mdelay (1000);

Printk ("Reboot failed - System halted\n");

While (1);

}

On the command line, enter the reboot command, but system is not reboot.

# reboot

SysRq: Emergency Remount R/O

EXT4-fs (mmcblk0p4): re-mounted. Opts: (null)

EXT4-fs (mmcblk0p6): re-mounted. Opts: (null)

Emergency Remount complete

Imx2-wdt imx2-wdt.0: Device shutdown: Expect reboot!

Restarting system

Last printk which gets into Klog is before cpu_proc_fin () function,

cpu_proc_fin() is call /arch/arm/mm/proc-v7.S

ENTRY(cpu_v7_proc_fin)

  mrc p15, 0, r0, c1, c0, 0 @ ctrl register

  bic r0, r0, #0x1000 @ ...i............

  bic r0, r0, #0x0006 @ .............ca.

  mcr p15, 0, r0, c1, c0, 0 @ disable caches

  mov pc, lr

ENDPROC(cpu_v7_proc_fin)

Why hang before cpu_proc_fin () function?how to  solve this problem?

[mrleo · Accepted solution]

sorry,uboot is add "ldo_active=on"

[mrleo]

Hi,all

Inl /arch/arm/mm/proc-v7.S cpu_proc_fin()

ENTRY(cpu_v7_proc_fin)

  mrc p15, 0, r0, c1, c0, 0 @ ctrl register

  bic r0, r0, #0x1000 @ ...i............

  bic r0, r0, #0x0006 @ .............ca.

  mcr p15, 0, r0, c1, c0, 0 @ disable caches

  mov pc, lr

ENDPROC(cpu_v7_proc_fin)

Comment out the following line of code will be ok

@ bic r0, r0, #0x0006 @ .............ca.

[fatalfeel]

Comment out the following line of code will be ok

@ bic r0, r0, #0x0006 @ .............ca.

////

I try and fail

[jimlentz]

I am seeing the same problem on MX6Q.

I don't understand WHY these lines need to be commented out, yes it fixes it -- but why?

Why isn't the Freescale  kernel repository reflect this change if it's needed?

I also don't understand the reference to the LDO being the reason. What does the LDO have to do with cache?

[agherzan]

Why this fix? Do we have an explanation on what is actually happening here? I encounter the same issue on a custom imx6q based platform.

[mrleo]

Hi agherazn,

Maybe is ldo_bypass will cause this issue, if you in uboot add "ldo_enabled=on" it is ok. reboot is will ok for you!

[raymondwang]

mx6q reboot implementation located at /arch/plat-mxc/system.c function arch_reset(char mode,const char* cmd).

Just look through arch_reset code, you can realize that mx6 reboot is achieved by watchdog output.

  On sabresd board, it use WDOG2 output to reset external PMIC. If your board does not reboot properly,you can

check your WDOG2 output pin config.

  On my board ,we use WDOG1 to reset external PMIC, so add extra code to support WDOG1 output is necessary.

  Hope these info can help you.

[Wlodek_D_]

Hello,

Thank you for your post, however please consider moving it to the right community place (e.g. i.MX Community ) to get it visible for active members.

For details please see general advice Where to post a Discussion?

Thank you for using Freescale Community.

[mrleo]

Thanks