The following document (sort of application note) discusses a delay line implemented in the Kinetis for an analogue input stream sampled (for example at 8kHz) by its ADC and saved to memory using DMA. At the same time, stored data in memory is transferred by DMA to a DAC output. All timing is controlled by the PDB (programmable Delay Block) without need for additional timers.
The result is a delay line with the delay between analogue input stream and analogue output stream depending on the buffer size used (eg.. 8k samples buffer giving 1s delay).
The delay line can operate with zero CPU intervention and continues operating even when the CPU is paused by a debugger.
In addition, the configuration of half-buffer interrupts shows how the buffer data can be processed - eg. to filter the stream, or to allow recording to an SD card or playing back analogue data from an SD card, or numerous other variations.
http://www.utasker.com/docs/uTasker/uTaskerADC.pdf (see chapter 2)
Anyone interested in seeing it in operation can load a binary image to their K60N512 tower or Kwikstik from http://www.utasker.com/SW_Demos.html#KINETIS_APP