VF5xx / Example of LPDDR2 Configuration

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VF5xx / Example of LPDDR2 Configuration

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soichiyamamoto
Contributor V

Hi, Please give me Example of LPDDR2 Configuration. Best regards, soichi yamamoto

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soichiyamamoto
Contributor V

Additional notes I think that "VyBrid supports LPDDR2, Therefore, I do the operation check with LPDDR2 as a device". Please give me LPDDR2 Configuration at that time. There are a great many registers setting DDRMC. Therefore, please help me. Best regards, soichi yamamoto

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alejandrolozan1
NXP Employee
NXP Employee

Hi,

Please accept our apologies for the delay.

I was able to get a code that might be helpful.

Unfortunately that is the only thing I could get for Vybrid.

Please let me know if that helps.

Best Regards,

Alejandro

1,913 Views
soichiyamamoto
Contributor V

Dear Alejandro,

Thank you for a reply.

The LPDDR2 Configuration is DDRMC = 200MHz.

I want use DDRMC = 400MHz

Please give me advice of necessary configuration register for clock 400MHz.

I am extremely grateful for your devoted support.

Best regards,

soichi


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soichiyamamoto
Contributor V

Dear Alejandro,

Thank you for a reply.

Please advise me.

Are the follows all right for the register to change for ”DDRMC = 200MHz  => 400MHz ” ?

If there is a register adjusting it elsewhere, please tell me the register.

Best regards,

soichi

registerlpddr2_200mhz_ss-silicon' ConfigurationDDRCK = 400MHz ConfigurationJEDEC
Parameter
Configuration ParameterregisterParameterHex ValueParameterHex ValueSymbolValue
DDRMC_CR020x00000014TINIT100ns)0x0014100ns)0x0028tINIT020ms
DDRMC_CR030x00009C40TINIT3200000ns)0x9C40200000ns)0x00013880tINIT3200us
DDRMC_CR040x000000C8TINIT41000ns)0x00C81000ns)0x0190tINIT41us
DDRMC_CR050x0000007D0TINIT510000ns)0x07D010000ns)0x0FA0tINIT510us
DDRMC_CR120x00000106WRLAT1(tCK)0x00013(tCK)0x0003WL1(tCK)
CASLAT_LIN3(tCK)0x00066(tCK)0x000CRL3(tCK)
DDRMC_CR130x0d020202TRC65ns)0x000D65ns)0x001AtRAS
tRPab
27ns-70us
18ns-27ns
TRRD10ns)0x000210ns)0x0004tRRD10ns
DDRMC_CR140x0a040209TFAW50ns)0x000A50ns)0x0014tFAW50ns
TWTR10ns)0x00027.5ns)0x0003tWTR7.5ns
TRAS_MIN45ns)0x000942ns)0x0011tRAS42ns
DDRMC_CR160x05020000TRTP10ns)0x00027.5ns)0x0003tRTP7.5ns
DDRMC_CR170x0036b005TRAS_MAX70000ns)0x36B070000ns)0x6D60tRAS70us
DDRMC_CR180x00000303TCKESR15ns)0x000315ns)0x0006tCKESR15ns
DDRMC_CR210x00040101TRCD_INT20ns)0x000418ns)0x0008tRCD18ns
DDRMC_CR220x00070000TDAL35ns)0x000733ns)0x000EtRPab (4-bank)
tWR
18ns
15ns
DDRMC_CR240x00000005TRP_AB25ns)0x000521ns)0x0009tRPab  8-bank21ns
DDRMC_CR260x0610001aTREF7760ns)0x06107760ns)0x0C20tREFI7.8us
TRFC130ns)0x001A130ns)0x0034tRFCab130ns
DDRMC_CR290x00000002TPDEX10ns)0x000210ns)0x0004tXP10ns
DDRMC_CR310x001C001CTXSNR140ns)0x001C140ns)0x0038tXSR140ns
TXSR140ns)0x001C140ns)0x0038tXSR140ns
DDRMC_CR660x004800c8ZQCL360ns)0x0048360ns)0x0090tZQCL360ns
ZQINIT1000ns)0x00C81000ns)0x0190tZQINIT1us
DDRMC_CR670x00000012ZQCS90ns)0x001290ns)0x0024tZQCS90ns
DDRMC_CR710x00000A00ZQRESET50ns)0x000A50ns)0x0014tZQRESET50ns
DDRMC_CR920x00010200TDQSCK_MIN5ns)0x00012.5ns)0x0001tDQSCK(min)2.5ns
TDQSCK_MAX10ns)0x00025.5ns)0x0003tDQSCK(MAX)5.5ns
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1,913 Views
soichiyamamoto
Contributor V

Hi, I was able to obtain a sample of 400MHzConfiguration from Local FAE. Thank you for support. soichi,

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alejandrolozan1
NXP Employee
NXP Employee

Hi Soichi,

I have been looking for the datasheet in the designer web page. But there is nothing, the one that fits the most is this one:


H9TKNNN1G

And the only information available are general specs:

Features

[ PoP ]

  • Operation Temperature
    - -30oC ~ 85oC
  • Packcage
    - 168-ball FBGA
    - 12.0x12.0mm2, 0.8t, 0.5mm pitch
    - Lead & Halogen Free

[ LPDDR2 S4B ]

  • VDD1 = 1.8V (1.7V to 1.95V)
  • VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30)
  • HSUL_12 interface (High Speed Unterminated Logic 1.2V)
  • Double data rate architecture for command, address and data Bus;
    - all control and address except CS_n, CKE latched at both rising and falling edge of the clock
    - CS_n, CKE latched at rising edge of the clock
    - two data accesses per clockcycle
  • Differential clock inputs (CK_t, CK_c)
  • Bi-directional differential data strobe (DQS_t, DQS_c)
    - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
    - Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation
    - Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation
  • DM masks write data at the both rising and falling edge of the data strobe
  • Programmable RL (Read Latency) and WL (Write Latency)
  • Programmable burst length: 4, 8 and 16
  • Auto refresh and self refresh supported
  • All bank auto refresh and per bank auto refresh supported
  • Auto TCSR (Temperature Compensated Self Refresh)
  • PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
  • DS (Drive Strength)
  • DPD (Deep Power Down)
  • ZQ (Calibration)

I will try to get it from them.

1,913 Views
soichiyamamoto
Contributor V

Dear Alejandro,

Thank you for a wonderful reply.

I am extremely grateful for your devoted support.

Please tell me the Parts number of LPDDR2 for reference.

Best Regards,

soichi

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alejandrolozan1
NXP Employee
NXP Employee

Hi,

Looking at the validation board schematic I can see this part number:H9TCNNN1GBMMVR-NEM

I hope that helps.

Alejandro

1,913 Views
soichiyamamoto
Contributor V

Dear Alejandro,  Thank you for a reply. Do you have H9TCNNN1GBMMVR-NEM's datasheet? If you have,please give me the LPDDR2's datasheet.  I am extremely grateful for your devoted support. Best Regards, soichi

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