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The frequency of MK60 twice low then expected

Question asked by Nataliya Doni on Aug 13, 2013
Latest reply on Aug 16, 2013 by Nataliya Doni

I'm creating the project with MK60FN1M0VLQ15. I use external clock 25MHz.

When I move from PEI mode to PEE mode 150 MHz, I have got MCGCLKOUT 75 MHz (on TRACE_CLKOUT 18,8 MHz, on FB_CLK 25MHz).

But I've expected 150 MHz.



VDIV0=0x02 (18), PRDIV=0x02 (3).


But I have got 150 MHz only when VDIV0=0x14 (36).


What is it? An error in datasheat or my error?

Please, help me to find a mistake!


This my code:

  MCG_C2 = 0;
  MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
  /* if we aren't using an osc input we don't need to wait for the osc to init */
   MCG_C5 = 0;
  while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear

  while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk

// Now in FBE

  // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
  MCG_C6 = 0x0;

// Set system options dividers 150 МГц
      //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/3, Flash clock= MCG/6
      // Set the VCO divider and enable the PLL , LOLIE=0, PLLS=1, CME=0, VDIV=18   
      MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(0x2); //M = 18  R =3 mcgoutclk=fext*m/r
      pll_freq = 150;
  while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set

  while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
// Now running PBE Mode
// Transition into PEE by setting CLKS to 0

// Wait for clock status bits to update
  while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};

// Now running PEE Mode
  MCG_C2|=0X80;// генерируется сброс при потере внешнего clk
return pll_freq;