Please tell me the method to hold data of DDR3 or LPDDR2 in LPSTOPx mode.
Please tell me the method to hold data of the internal RAM in LPSTOPx mode.
Note regarding DDR3 Self-Refresh mode when Vybrid in LPStop modes:
* Not supported - as per Datasheet, DDR_RESET and DDR_CKE pins are in High-Z state in these modes.
* To add such support, following board modifications required:
1. Depopulate R107,
2. Add 10K pull-up to VCC_1V5 rail on DDR_RESET net,
3. Add 10K pull-down to GND rail on DDR_CKE net.
Regards, Naoum Gitnik.
Dear Naoum, Does IOConfiguration maintain it in LPSTOPx mode.? Best Regards, soichi yamamoto
Naoum Gitnik please continue with the follow up on this case.
Unfortunately, Vybrid is designed so that the pins' states are not controlled/retained in the LPStop modes; this is why external resistors are required (otherwise I would recommend you relevant settings...).
Dear Naoum, Thank you for reply. Please tell me states of pin in LPStop modes? input or output? states of WKPU Pin ? Best regards, soichi
Dear Naoum, Please tell me about the status of IO except the DDR. Best Regards, soich,
This information is in the "14.3 Low-power modes" section, in "Table 14-2. Power gating and clock gating overview".
Briefly, they are in the High-Z state (the WKUP ones described separately, as I mentioned earlier - also see "14.3.7 Interrupt connectivity").
All the idea of LPSTOP modes is to save as much power as possible (this is why they are called "power-gating"), so a lot of power domains on the die are simply "powered off".
Thank you for reply.
What is High-Z state?
Which Is IO Input or output?
Which Is Logic High or Low?
The definition is here - High impedance - Wikipedia, the free encyclopedia.
Is Default of Kintis Pin same as High-Z state?
The default for most Kinetis pins are to be tri-stated out of reset.
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