I have an HDMI receiver that can output 12-bit CCIR-656. The signals are connected to the i.MX6q as follows:
VID_DATA00 -> IPU1_CSI0_DATA08
VID_DATA01 -> IPU1_CSI0_DATA09
VID_DATA02 -> IPU1_CSI0_DATA10
VID_DATA03 -> IPU1_CSI0_DATA11
VID_DATA04 -> IPU1_CSI0_DATA12
VID_DATA05 -> IPU1_CSI0_DATA13
VID_DATA06 -> IPU1_CSI0_DATA14
VID_DATA07 -> IPU1_CSI0_DATA15
VID_DATA08 -> IPU1_CSI0_DATA16
VID_DATA09 -> IPU1_CSI0_DATA17
VID_DATA10 -> IPU1_CSI0_DATA18
VID_DATA11 -> IPU1_CSI0_DATA19
VID_HSYNC -> IPU1_CSI0_HSYNC
VID_VSYNC -> IPU1_CSI0_VSYNC
VID_EN -> IPU1_CSI0_DATA_EN
VID_CLK -> IPU1_CSI0_PIXCLK
The receiver supports embedded sync/timings. My understanding from the i.MX6QRM is that I should set the following to indicate 12-bit BT.656 with embedded signalling:
IPU1_CSI0_SENS_CONF = 0x00002a20:
EXT_VSYNC=0 (Internal VSYNC Mode)
DATA_WIDTH=5 (12bit) (assuming this means width of CCIR data when using CCIR and not 'bits per color')
SENS_DATA_FORMAT=2 (YUV422 UYVY) (not sure how this relates to CCIR data)
SENS_PRTCL=2 (CCIR progressive mode)
I find I am not getting frame interrupts (prp_enc_callback) and I believe its because my data bus is not being interpreted correctly such that I don't have frame/field markers being properly decoded.
My questions are:
1. Is there any reason why the i.MX6Q CSI couldn't handle 12bit CCIR-656? If no, do I have the data bits from the receiver connected properly to the CSI? (ie if I tell the CSI 12-bit, is the MSB DATA19?)
2. If I am using BT.656 mode (i.MX6QRM 220.127.116.11.3) with embedded timing/signalling I should only need the data signals, and clock (and can remove HSYNC/VSYNC/EN) correct?
3. Is there any advantage at all in using gated clock mode over embedded signalling/timing?
4. When using BT.656 mode what os the meaning of SENS_DATA_FORMAT?
5. When using BT.656 mode with embedded syncs is setting EXT_VSYNC=0 the only register setting needed?