External Oscillator Allowed ?

[ChrisNielsen]

I need to maintain tight ppm control over the main input high-speed clock source so I want to use an oscillator, not a crystal.  FXOSC on the Vybrid tower board uses a 24.000 crystal (the load caps and pcb stray cap cause too many variables for my application).

Is it possible to use a 24.000 MHz oscillator as the main input clock source?

The datasheet is unclear on this point.  It is also unclear what I/O voltages are allowed if an oscillator is supported.  Has any testing been done with an external oscillator?

Thanks, Chris

[ChrisNielsen]

A few clarification questions:

The Rev 5 DS page 105 states:

The crystal can be eliminated if an

external 24 MHz oscillator is available in the system. In this

case, XTAL must be directly driven by the external oscillator

and EXTAL floated. The XTAL signal level must swing from

~0.8 x DECAP_V11_ LDO_OUT (1.1V typ) to ~0.2 V.

Resulting math gives Min = ~0.2V, Max = ~0.88V

The Rev 5 DS Table 62 on page 77 states:

VIH XTAL pin input high voltage — Min = 0.75 x Vdd, Max = Vdd+0.3

VIL XTAL pin input low voltage  — Min = Vss-0.3, Max = 0.25 x Vdd

1. VDD=1.1 V +/-10%, TA = -40 to +85 °C, unless otherwise specified.

Resulting math gives Min = 0.3V, Max = ~1.4V

>>> My question is which is correct?  What is the true VIH max and VIL min spec for the XTAL pad?

Would it meet the XTAL pad voltage requirements if I purchased a 1.8V or 3.3V oscillator and passed its output through a voltage translator whose output was powered by DECAP_V11_ LDO_OUT?

Thanks, Chris

[naoumgitnik · Accepted solution]

Dear Chris,

As mentioned earlier, the Datasheet is still being finalized (sorry for all these discrepancies), so, please, take the below information and concerns into account:

1.       According to the Vybrid IC design data, voltage on the low-voltage “XTAL” IC pad (different than a regular GPIO) shall not exceed 1.1V.

2.       Getting data for the minimum value needs additional time; however, it looks like this special-type pad does not like levels beyond the relevant power rails, therefore I would not recommend going below the GND level.

3.       You may use an external high-quality clock oscillator, and then use a level-shifting IC to keep the low-voltage clock within the 0…1.1V limits (both powered from really clean power sources to keep your clock’s quality high).

4.       For the level-shifting IC, though, I would not recommend using DECAP_V11_ LDO_OUT (not intended for that) for the below reasons:

* Quite possibly its output power capability might be insufficient for additional load (a digital IC operating at 24MHz),

* Even if no power capability problem, the switching noise generated on this power rail might hurt performance of our internal analog blocks (see the “Power Supply” diagram for details).

5.       For a level-shifting IC, I would recommend using a separate clean voltage source, e.g. a linear voltage regulator.

6.       Using passive level shifting (e.g. a resistor divider) has its advantages, but I have only used it for frequencies noticeably lower than 24MHz and cannot comment on that.

Sincerely yours, Naoum Gitnik.

[naoumgitnik]

Dear Chris,

Yes, the Datasheet table only provides the VIH and VIL values for the XTAL pin without clearly stating that these requirements are for an external oscillator. There is a typo (to be fixed), though, in the comment right after the table that Vdd = 3.3V; it is incorrect: Vdd = 1.2V as in the rest of the document.

Unfortunately, we cannot recommend any 1.2V-powered 24MHz oscillator for your design, since the product validation has been done using a bench frequency generator.

Depending on your design specifics, you may bypass and even disable the on-chip oscillator (see the Reference Manual for details).

Sincerely yours, Naoum Gitnik.