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Flexbus delay

Question asked by Filip Dossche on May 6, 2013
Latest reply on May 14, 2013 by Filip Dossche



I am using an MCF54415 processor running on a Netburner MOD54415 module.

I have an application where I need to read an AD converter value at a rate of 128 nanosconds.

The processor is set up to run at 250MHz and the FB_CLK runs at 125 MHz.

I have checked that and it does produce a 125 MHz signal on the FB_CLK pin.

I have set up chip select 1 to be accessed within range 0x0200000...0x0200FFFF


According to the documentation in the reference manual the minimum total time to execute a read transfer from the specified address is 32 nanoseconds (4 FB_CLK cycles). to make it work OK with the AD converters I need to introduce 1 wait cycle during the generation of the CS signal which would put the total cycle time at 40 ns (i.e: 5 cycles).


To test how long it really takes I have put the single instruction that does the transfer in between two other which each in turn toggle an RGPIO pin.

Once every second The RGPIO pin is first toggled 10 times, then the transfer instruction is executed and the RGPIO pin is toggled another 40 times.


This the small section of code:


   asm(" move.w %d5,%a5@");     // Toggle pin

   asm(" move.w %d5,%a5@");     // Toggle pin

   asm(" move.w %a0@,%d0");     // transfer from AD


   asm(" move.w %d5,%a5@");     // Toggle pin
   asm(" move.w %d5,%a5@");     //Toggle pin


The RGPIO toggling gives me a very nice trace to use my scope with and test how fast things are running.

The subsequent toggle instructions consistently and repetitively make the state of the pin change every 16 nanoseconds.

Oddly enough it seems to take at least 80 nanoseconds to execute the single transfer instruction, that is the smallest amount of time I can measure between the last toggle instruction before the transfer and the next one after it.

That puts the total number of bus cycles for the transfer operation at 10 instead of the expected 5.

The flexbus is definitely running at 125 MHz because as I increase or decrease the number of wait states during the generation of the CS signal it gets longer or shorter with 8 nanoseconds/wait state.


Anyone have any ideas or suggestions what might be going on ?