QD4 PTA4 and PTA5

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QD4 PTA4 and PTA5

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Cram
Contributor III


Dear all,

 

I'm using a S9S08QD4 and I need to use the PTA4 as an output and PTA5 as an Input. No problem with it at all in normal operation.

 

I'm using PTA5 to poll a voltage level, via a pull-up resitor 4k7, when the voltage at PTA5 goes to 0V I need to turn on the PTA4 ouput as a 1Hz square wave.

 

PTA4 is driving a BC817 via RB 4k7 and a pull-down of 47k.

 

Drive Strengh is ON for PTA3 and PTA4.

 

I found these problems:

 

PROBLEM1:

 

With RB 4k7 I can program the target I need to increase that value up to 20k, anybody knows why?

 

PROBLEM2:

 

Voltage at PTA5 is 5V and then turn on the uP and then the voltage at PTA5 goes to 0V no problem. But if volatge at PTA5 is 0V and the turn on the uP it becomes stuck somewhere with no output generation at PTA4 ana DC level euqls to 3V1. Could be a problem with the BKG instruction or Hw?

 

I checked the softusing for a while another pin (PTA2) and seems to work properly.

 

Here my init code for the PORTS and BKG

 

void periphInit (void){


  asm SEI;        //disable interrupt mask

  SOPT1 = 0x92;         //0x92 BKG 0X90 No BKG
  SOPT2 = 0x00;
 
  SPMSC1 = 0x01; //1C 
  SPMSC2 = 0x00;                                     
 
  /*  System clock initialization */
 
  ICSTRM = *(unsigned char*far)0xFFAF; /* Initialize ICSTRM register from a non volatile memory */
  ICSSC = *(unsigned char*far)0xFFAE;  /* Initialize ICSSC register from a non volatile memory */
 
 
  /* Initialization of the ICS control register 1 */
  /* Initialization of the ICS control register 2 */
  ICSC1 = 0x06;                        /* ICSC1: CLKS=0,IREFSTEN=0 */
  ICSC2 = 0x00;                        /* ICSC2: BDIV=1,LP=0 */
 

  //I/O

 

  PTASE=0x00;

  PTADS=0x18;     // DS activat per a PTA3 i PTA4

  PTAPE=0x00;     // no pull up

 

  PTAD=0x00;      //les sortides a zero logica NPN

  PTADD=0x18;     //Codifiquem

 

 

  //CAD

 

  ADCSC1=0x1F;      //disabled

  ADCSC2=0x00;

  ADCCFG=0x18;

  APCTL1=0x07;      //Ch0+Ch1+Ch2

 

 

  // MTIM ( Base de Temps : 1,008ms)

 

  /* TPMSC: TOF=0,TOIE=0,CPWMS=0,CLKSB=0,CLKSA=0,PS2=0,PS1=0,PS0=0 */

  TPMSC = 0x00;                        /* Stop and reset counter */

  TPMMOD = 0x3E;                       /* Period value setting */

  (void)(TPMSC == 0);                  /* Overflow int. flag clearing (first part) */

 



  clrWD();

}

 

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bigmac
Specialist III

Hello Marc,

Your problem is possibly due to the external circuitry connected to PTA4 providing a pull down.  When a POR or any other reset occurs, this will cause the device to enter background debug mode.  Without a Multilink connected, nothing will then happen and the device would remain in limbo.  This occurs before any code is executed, prior to PTA4 being enabled as a general purpose output pin.

If the external transistor is a NPN type, the base circuit will be providing the pull-down during POR.  One solution may be to use a MOSFET as the buffer, and provide an external, high value pull-up resistor at the gate connection.

Another possibility is to use a PNP bipolar transistor, with emitter connected to Vdd.  If you require that the transistor remain non-conducting during and subsequent to the POR process, make sure that you set PTA4 output high, prior to enabling as a GP output.

Regards,

Mac

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bigmac
Specialist III

Hello Marc,

Your problem is possibly due to the external circuitry connected to PTA4 providing a pull down.  When a POR or any other reset occurs, this will cause the device to enter background debug mode.  Without a Multilink connected, nothing will then happen and the device would remain in limbo.  This occurs before any code is executed, prior to PTA4 being enabled as a general purpose output pin.

If the external transistor is a NPN type, the base circuit will be providing the pull-down during POR.  One solution may be to use a MOSFET as the buffer, and provide an external, high value pull-up resistor at the gate connection.

Another possibility is to use a PNP bipolar transistor, with emitter connected to Vdd.  If you require that the transistor remain non-conducting during and subsequent to the POR process, make sure that you set PTA4 output high, prior to enabling as a GP output.

Regards,

Mac

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Cram
Contributor III

Hi BigMac,

You are right, yesterday evening I was thinking in the same direction, the PTA5 was tied to GND and PTA4 via de diode-union (base-emitter) from the NPN makes the app. crash.

I removed the base resitor and leave the PTA4 without connection an no problem, then I use a FET transistor and no problem!

So thanks for you support!

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