Hi all, the DDR clock of i.mx6 is 528MHz on boot time, but I want to change it to lower(may be 400MHz).
I read the Datasheet and found the below introduction:
18.104.22.168.3 PLL clock change
If software wants to change pll clock output of a specific pll, or if software wants to stop
a specific pll, then software needs first to move all the clocks generated from this pll to
another pll which is not changed.
This should be done via the glitch less mux's for the clocks which cant be stopped (core
and bus clocks). Procedure of PLL clock change is described in anatop module spec.
But I can't found the "anatop module spec".
By the way, in i.mx5,the clock is configure int the file of "lowlevel_init.S" by the macro of "init_clock" & "setup_pll pll, freq",
But in i.mx6,the macro of "setup_pll pll, freq" is empty and "PLL1, PLL2, and PLL3 are configured by ROM", so I have no idea of how to change DDR clock of i.mx6.
If anyone can help me please?