iMX6 RGMII + ENET_REF_CLK/ENET_TX_CLK

[tarterkit_ru]

As see on shematic few iMX6 boards, RGMII PHY put to MAC 125MHz to ENET_REF_CLK/ENET_TX_CLKENET_TX_CLK pin.

What it for?

I can't see any describe of this in manuals and RGMII not require this signal.

[fei_liu]

In RGMII Mode, only the pin "ENET_REF_CLK" could used as 125M reference clock input.

The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration).

In RMII Mode, only two pins "GPIO_16" and "RGMII_TX_CTL" could be used as the 50M reference clock. The clock source could be from external oscillator or internal PLL, need software configuration. Please refer the document "I.MX6 Hardware Development Guide", Chapter 11.

[yinchunhui]

hello Fei Liu

You said "The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration)."

I want to ask how to routed from GPIO_16?What is the detail configuration?

Now I can generate the 125M clock at the GPIO_16.

Thank you very much

[fei_liu]

ENET_REF_CLK is the input pin for RGMII reference clock, so if you want to use GPIO_16 to provide the 125M clock, you should connect GPIO_16 to ENENT_REF_CLK, and be careful, the voltage level might be different, you might need an level shift.

[yinchunhui]

thank you very much!

But I see you say"need software configuration",is there any method though software?

[fei_liu]

The software configuration is just for outputting 125M on GPIO_16, since you have already done, no additional operations or configurations are needed.

Best regards,

Frank Liu

[yinchunhui]

ok,I know,thank you very much!

[MaxChou]

Hi Fei Liu

We follow "I.MX6 Hardware Development Guide", Chapter 11,

and modify below pin for RMII interface

////////////////

MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN,

MX6Q_PAD_ENET_MDIO__ENET_MDIO,

MX6Q_PAD_ENET_MDC__ENET_MDC,

MX6Q_PAD_ENET_TX_EN__ENET_TX_EN,

MX6Q_PAD_ENET_TXD0__ENET_TDATA_0,

MX6Q_PAD_ENET_TXD1__ENET_TDATA_1,

MX6Q_PAD_ENET_RXD0__ENET_RDATA_0,

MX6Q_PAD_ENET_RXD1__ENET_RDATA_1,

MX6Q_PAD_ENET_RX_ER__ENET_RX_ER,

MX6Q_PAD_RGMII_TX_CTL__ENET_ANATOP_ETHERNET_REF_OUT,

//////////////////

but we still have problem on RMII,

is anything else I should check in the kernel driver ??

How to config below pins ? Should I modify it to other function ??

/////////////////////////////////////////////////// 
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,

/////////////////////////////////////////////////////

Sincerely,Max

[DuanFugang]

Kernel driver don’t support RMII, but we have patch for this. （You can email to me to get it： b38611@freescale.com）

Don’t care about RGMII pad control.

[DuanFugang]

Attached the patch for RMII base on kernel 3.0.35.

[liguoqing]

Hi Duan

How can i use RMII on imx6D on kernel 4.1.15?

[marcocavallini]

For RMII you need to set 50Mhz clock for enet, the best option would be to set it in u-boot using the following call and have the clock already set in the kernel

enable_fec_anatop_clock(ENET_50MHZ);‍‍

[mchaplet]

Thanks for this patch !

I also use LAN8720 and RMII connection to it from a IMX6S and it works well in U-Boot but last kernel 3.10.17 from imx git seems to disable 50MHz PLL.

How to force it in DTS ?

I've yet tried to replace clks190 - "ptp" by "enet_ref" in fec controller description (imx6qdl.dtsi) without success.

Thanks,

Martin

[marcocavallini]

Hi,

is it working your i.MX6S kernel 3.10.17 with LAN8720 and RMII connection?

[shabeerbadarudh]

sorry for the late reply.

Yes, it was worked in our platform. (i.MX6S kernel 3.10.17 with LAN8720 and RMII)

[marcocavallini]

Here it is at last ;-)

Cordiali Saluti / Kindest Regards / Mit freundlichen Grüßen

--

Marco Cavallini | KOAN sas | Bergamo - Italia

embedded and real-time software engineering

Phone:+39-035-255.235 - Fax:+39-178-22.39.748

[shabeerbadarudh]

Hi Martin,

We are also facing the same issue. Did you have any luck in 3.10.17?

[lukascaha]

hello,

we have similar problem with custom board with MX6S/DL. PHY is LAN8720 and i u-boot works ok.

In kernel, iomux and clock generated by gpio_16 is ok.

I don't understand - kernel driver don't support RMII, but on MX6SL dev board (and processor) is only RMII.

I know this is allmost another processor, but changes in u-boot are inpired by mx6slevk.c

Ist about RMII support for MX6S/DL/Q ?

For what kernel branch is patch applicable - is RMII support better in some branches - I use imx_3.0.35_1.1.0

thank

Lukas

[MaxChou]

Hi Fugang Duan

it is sloved, thanks!!

[JorgeRama_rezRi]

Hi Pavel,

There are 3 ways to supply the ENET clock. Please see chapter 11 of the attached, I think it will clarify.

Best regards.

Jorge.

[tarterkit_ru]

Thanks, this document told about GPIO_16 refclock connections, but sabresd, sabresdlite boards use ENET_REF_CLK pin for reference clock and this document don't have any for it ...