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i.MX6 PCIe: CFG TLP generation.

Question asked by Tony Riederer on Nov 26, 2012
Latest reply on Jan 31, 2013 by Eric Nelson
Branched to a new discussion

Hello,

 

We are attempting to use the i.MX6 with a generic PCIe switch. After reviewing the PCIe controller documentation (Chapter 48 of the RM, Rev 0) we have made the following changes to the linux kernel driver:

  • We expanded the iATU region 1 mapping from 1M to 2M (1MB per bus)
  • We enabled address shift mode in PCIE_PL_iATURC2.
  • We are constructing our untranslated addresses using the fields specified in Table 48-23.  This required changing the macros (pcie.c) which did not match either mapping defined in the RM. The existing code works with a single device because the BDF value is always 0.

 

With or without these changes, we are able to access the CFG space of the upstream switch port (Bus 1, BDF = 0.0.0 )  including the PCIe specific registers. However, we cannot successfully read the CFG space for the downstream ports associated with bus 2 (BDF = 1.0.0).

 

The behavior we are seeing is:

  • Changing the Bus and Device fields in the untranslated address has no discernible effect on the CFG read/write cycle. We always get back the Bus 1 Device 0 values regardless of the D27:15 values.
  • Changing the function number to non-zero causes an abort. This is not expected as the RM states that the function number in the outbound TLP is derived from PCIE_PL_iATURC1 D22:20
  • Accessing bus 1 (BDF = 0.0.0) registers >= 0x400 causes an abort.

 

Any clarification on how to configure the imx6 to generate the proper CFG TLP would be greatly appreciated.

 

Thanks,

Tony

 

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