Ned Konz

i.MX53: How to move VGA external HSYNC and VSYNC signals to different pins?

Discussion created by Ned Konz on Jul 5, 2012
Latest reply on Sep 28, 2014 by Frank Chen

We have a new CPU board designed with the i.MX537 .

We're using the WEIM to talk to an FPGA, but also need to have a VGA display connected.

So we need to change the pins used for output of the HSYNC and VSYNC external signals (the QSB and Linux driver are set up to use EIM_OE and EIM_RW as the HSYNC and VSYNC output pins, but we need both of those as EIM signals instead).

Existing code outputs HSYNC and VSYNC signals on:
HSYNC: DI1_PIN7 = EIM_OE
VSYNC: DI1_PIN8 = EIM_RW

The existing code uses these counters (these names are from the OBDS code; 7 and 8 are used but not named; I added names for them):

DI_COUNTER_BASECLK 0
DI_COUNTER_IHSYNC 1
DI_COUNTER_OHSYNC 2
DI_COUNTER_OVSYNC 3 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_ALINE 4 (depends on DI_COUNTER_OHSYNC and DI_COUNTER_OVSYNC)
DI_COUNTER_ACLOCK 5 (depends on DI_COUNTER_ALINE)
(unused) 6
DI_COUNTER_OUT_HSYNC 7
DI_COUNTER_OUT_VSYNC 8 (depends on DI_COUNTER_IHSYNC)

We'd like to use these pins for HSYNC and VSYNC output:

HSYNC: DI1_PIN4 = EIM_DA15 (ALT4)
VSYNC: DI1_PIN6 = EIM_CS1 / GPIO2_24 (ALT3)

Now, since the existing code uses counter #4, I have to move the use of this counter to one of the unused counters. The remaining counters are 6, 7, and 8.

Because a counter can only refer to a counter with lower number, I have to maintain these relationships:

DI_COUNTER_OVSYNC > DI_COUNTER_IHSYNC
DI_COUNTER_ALINE > DI_COUNTER_OHSYNC
DI_COUNTER_ALINE > DI_COUNTER_OVSYNC
DI_COUNTER_ACLOCK > DI_COUNTER_ALINE
DI_COUNTER_OUT_VSYNC > DI_COUNTER_IHSYNC

So I'd like to set it up like this:
DI_COUNTER_BASECLK 0
DI_COUNTER_IHSYNC 1
DI_COUNTER_OHSYNC 2
DI_COUNTER_OVSYNC 3 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_OUT_HSYNC 4
(unused) 5
DI_COUNTER_OUT_VSYNC 6 (depends on DI_COUNTER_IHSYNC)
DI_COUNTER_ALINE 7 (depends on DI_COUNTER_OHSYNC and DI_COUNTER_OVSYNC)
DI_COUNTER_ACLOCK 8 (depends on DI_COUNTER_ALINE)

 

So I have to move:

DI_COUNTER_OUT_HSYNC from 7 to 4
DI_COUNTER_OUT_VSYNC from 8 to 6
DI_COUNTER_ALINE from 4 to 7
DI_COUNTER_ACLOCK from 5 to 8

I've managed to get HSYNC and VSYNC to come out the right pins by changing the setup of the DI counters, but so far have been unable to get video to come out at the same time.

One problem that I've found is that the DC template refers (I think) to a waveform generator.
The SYNC bits (low order 4 bits in the DC template microcode words) hold the number of a generator.

From the Linux code (rel_imx_2.6.35_11.09.01 tag, drivers/mxc/ipu3/ipu_disp.c, line 1487):

// _ipu_dc_write_tmpl(ipu,word,opcode,operand,map, wave, glue,sync,stop)
_ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
_ipu_dc_write_tmpl(ipu, 3, WRG, 0, map, SYNC_WAVE, 4, 5, 1);
_ipu_dc_write_tmpl(ipu, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);

The WAVEFORM bits point to the DI1_DW_GEN_<i>; in this case the value written to the template is a 1 (SYNC_WAVE=0). So we're referring to DI1_DW_GEN_0.

I don't know whether the "sync" argument to _ipu_dc_write_tmpl() is actually the number of a DI waveform generator counter (that is, DI_COUNTER_ACLOCK), but when I changed my test code to refer to my new DI_COUNTER_ACLOCK (8 instead of 5), I still didn't get any output out of the R/G/B pins.

Any idea what I can do to make this work?

Thanks...

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