First, some background on the circuit: A periodic interrupt occurs which asserts /IPL2 through /IPL0 accordingly to request a level 1 interrupt. When /AS goes low and FC2,FC1,FC0 are high, /VPA is pulled low. It remains asserted until any of /AS or FC2,FC1,FC0 are negated. The 68000 always terminates the cycle by pulling /AS high after the variable cycle delay; this isn't an issue of /VPA being negated too early.
I get a shorter cycle time depending on what the 68000 is doing; e.g. executing NOPs gives 26 cycles, waiting in a STOP #$2000 condition tends to give 32 cycles, and so on.
I've monitored all the other signals and there seems to be nothing that would impact the timing, I'm assuming this is some kind of internal decision the 68000 makes. But I don't know the criteria involved.
The exact timing for an interrupt acknowledge cycle looks like this:
1. Finish executing current instruction
2. Stack PCL at SSP-2 (8 cycles for RAM access)
3. Interrupt acknowledge cycle (26/32/44 cycles, variable)
4. Stack SR at SSP-6 (8 cycles for RAM access)
5. Stack PCH at SSP-4 (8 cycles for RAM access)
6. Read interrupt vector low word (10 cycles for ROM access)
7. Read interrupt vector high word (10 cycles for ROM access)
8. Execute first instruction from ISR
My concern is that the the periodic interrupt has some jitter introduced between each interrupt as the the time is off by a variable amount of cycles per interrupt, which I need to eliminate.
Rather than rework the design I'd like to know why the 68000 does this even if it's a limitation of the CPU and something I can't control. (for example, maybe the specification of 44 cycles indicates a maximum; rather than the absolute count?)