brett swimley

MCF547x FlexBus Timing

Discussion created by brett swimley on Sep 29, 2006
Latest reply on Oct 24, 2006 by brett swimley
I was hoping that someone could comment on the Timing diagrams provided in the MCF547x Reference Manual.

We are interfacing to an FPGA using the FlexBus, and are finding that the signal timings specified do not seem to be correct.

Some specifics:

1) Dotted lines indicated in the timing diagrams represent signal timing when internal termination is used (Auto Acknowledge = 1). Our observations are that the dotted line timings are not observered, but rather the solid line timiings (which are supposedly only for Auto Acknowledge = 0) are the timings in place.

2) We are attempting to do burst mode read DMA transfers from the FlexBus. Our FlexBus is set for 2 wait states for the initial transfer, but then we want to swap over to 0 secondary wait states (eg WS = 2, SWSEN = true, SWS = 0). We also have ASET = 0, RDAH = 0, WRAH = 0, AA = 1, PS = 0 (32 bit), BEM = 0, BSTR = 1, and I have tried BSTW = 0 and = 1.

Referencing the timings, we would expect CS to be active for a maximum of 7 clock cycles (when you take into account the additional 2 wait states we require at the beginning of the transfer). What we are observing is that CS is active for 12 clock cycles.

I can provide more detailed information if required. Can anyone comment on this timing diagram discrepancies?

Best Regards,

Brett Swimley