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Kinetis SPI Master Clock Polarity after Init

Question asked by Alessandro Vagniluca on Feb 16, 2012
Latest reply on Dec 18, 2016 by Steven Graves

I am developing my application on Kinetis K60 with CodeWarrior 10.1 with ProcessorExpert 5.1 and MQX 3.7.

I need to drive an SPI bus in master mode, so I use the SPIMaster_LDD embedded component.

 

I initialize clock polarity as HIGH and clock phase as CHANGE ON LEADING EDGE.

 

But after the execution of the SPI_Init() function the CLK pin is at LOW level. Why? The clock line idle state should be high.

 

For this reason, my first SPI Master transaction to the slave device (which requires a high clock idle state) always fails.

However, after the first SPI transaction the CLK pin remains high, so all the subsequent SPI transactions are good.

 

As a workaround, I make a dummy SPI transaction of a single data byte after the SPI_Init() function call and then I can get all the real subsequent transactions to work properly.

 

Does the Kinetis SPI peripheral initialization make the CLK pin output the correct idle level set by the chosen clock polarity?

 

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