I2S Buffer not processed yet

[mrichardson23]

Hello,

I am running into the error on the RT685 using the audio evaluation kit of kStatus_I2S_Busy when I attempt to transmit data on flexcomm 4.  My initialization of this bus is done at boot:

const i2s_config_t FC4_I2S_TX_config = {
  .masterSlave = kI2S_MasterSlaveNormalMaster,
  .mode = kI2S_ModeDspWsShort,
  .rightLow = false,
  .leftJust = false,
  .sckPol = false,
  .wsPol = true,
  .divider = 2,
  .oneChannel = false,
  .dataLength = 32,
  .frameLength = 256,
  .position = 0,
  .watermark = 4,
  .txEmptyZero = true,
  .pack48 = false
};
dma_handle_t FC4_I2S_TX_TX_Handle;
i2s_dma_handle_t FC4_I2S_Tx_Handle;

static void FC4_I2S_TX_init(void) {
  /* Flexcomm I2S initialization */
  I2S_TxInit(FC4_I2S_TX_PERIPHERAL, &FC4_I2S_TX_config);
  /* Setup secondary channel 1 */
  I2S_EnableSecondaryChannel(FC4_I2S_TX_PERIPHERAL, kI2S_SecondaryChannel1, false, 64U);
  /* Setup secondary channel 2 */
  I2S_EnableSecondaryChannel(FC4_I2S_TX_PERIPHERAL, kI2S_SecondaryChannel2, false, 128U);
  /* Setup secondary channel 3 */
  I2S_EnableSecondaryChannel(FC4_I2S_TX_PERIPHERAL, kI2S_SecondaryChannel3, false, 192U);
  /* Enable the DMA 9 channel in the DMA */
  DMA_EnableChannel(FC4_I2S_TX_TX_DMA_BASEADDR, FC4_I2S_TX_TX_DMA_CHANNEL);
  /* Set the DMA 9 channel priority */
  DMA_SetChannelPriority(FC4_I2S_TX_TX_DMA_BASEADDR, FC4_I2S_TX_TX_DMA_CHANNEL, kDMA_ChannelPriority3);
  /* Create the DMA FC4_I2S_TX_TX_Handle handle */
  DMA_CreateHandle(&FC4_I2S_TX_TX_Handle, FC4_I2S_TX_TX_DMA_BASEADDR, FC4_I2S_TX_TX_DMA_CHANNEL);
  /* Create the I2S DMA handle */
  I2S_TxTransferCreateHandleDMA(FC4_I2S_TX_PERIPHERAL, &FC4_I2S_Tx_Handle, &FC4_I2S_TX_TX_Handle, NULL, NULL);
}

Am I doing something wrong here? The clock for FC4 is attached to the audio pll and all of the pins are configured for I2S functionality.

[Frank_Kim]

@EdwinHz, thank you for follow-up. I will continue to follow up with Matt. Thank you.

Regards,

Frank 

[EdwinHz]

Hi @mrichardson23,

It is my understanding that you are trying to implement "TDM and DSP modes with 1 SCK pulsed WS" as seen on "Fig 73." of the Reference Manual, is this correct? If so, please refer to the "mimxrt685audevk_i2s_dma_tdm" example code from our SDK, since it exemplifies how to setup this case. If fact, from a quick look into this example, I believe it has the same initialization configuration structure, except the example changes the "tx_config.position" to "1".

BR,
Edwin.

[mrichardson23]

Thanks, @EdwinHz .  I have done that.  I am currently building off of the playback-record example and all of that is functional.  I need to add FC4 and 5 for additional I2S busses.  So, can you tell me what might be going on where the bit clock is ticking at the expected rate but the WS clock is not right?  Could this be a hardware configuration issue?

[mrichardson23]

mrichardson23_0-1697124308836.png

Here is the description of the Flexcomm interface from the RT-600 manual - based on this, why is the bitclock correct but the ws clock not?

[mrichardson23]

I have checked the config and fifo registers.  In operation, they both look good.  CFG1 is 2039997 and the  FIFOCFG register is 4133.  On the board I have JP42 set to 2-3.  I can't see anything I am doing wrong here.  Could R79 be creating an issue here for me?

[mrichardson23]

New twist - bit clock looks good but the frame clock is running at the same rate:

mrichardson23_0-1696457594198.png