I'm using FLEXIO2 to send out 4-bit values. I have all of the shifters (7:0) linked together, so a "minor loop" traversal (one DMA burst) fills all 8 32-bit shiftbufs (32 bytes or 64 of my 4-bit values).
The DMA destination address is SHIFTBUF0 and the Destination Modulo is 32 bytes (so the second transfer should also load into SHIFTBUF0-7).
The source address is an array of uint_32_t (sendData) and the Source Modulo is 0.
So the intent is for each DMA transfer to copy 32 bytes (64 4-bit values) from successive 8 32-bit words of "sendData" to the 8 ShiftBufs. When the shifting starts, the Shiftbufs are transferred to the Shifters and shifting begins. Presumably, the DMA fills the Shiftbufs with the next 8 32-bit words from the "sendData" array.
I'm seeing the first 64 4-bit values shift out as expected, but the next 64 are a repeat of the first 64, and the 64 following that are also a repeat of the first 64, etc. I'm assuming that additional DMA requests are being issued after the first set of data (first 8 32-bit words) are loaded into the Shifter registers from the ShiftBuf registers that received the first DMA transfer.
It's as though the source DMA address goes back to the beginning of the array instead of marching through the uint_32_t array... OR... No new DMA requests are generated, and the shifters are reloading values from the ShiftBuf registers (that still have the same data).
Did I miss a setting? Not sure how to debug this...
Thanks!
