I have an issue where data is apparently only being written to memory when the code is stepped in the disassembly view of the debugger.
It feels like a cache coherency thing, but I can't imagine how, since I'm not using any DMA etc. The CPU is simply reading and writing the on-chip memory.
The code simply looks like this:
memset( check, 0, sizeof check );
flash::read( flash::ADDR_SERIAL_NUMBER, check, sizeof check );
Inside read() it's just
uint8_t* dst = (uint8_t*)data; dst[rxi] = rx;
If I step through that in the disassembly, I can see the strb instruction write the data. But if I just let it run over the whole read(), nothing is written to check[]. It's not incorrect data; it's whatever data is there before the function call.
This seems to happen more when the amount of data read is small, which again feels like a cache thing (larger reads knocking out cache lines).
I've experienced the same with the data array in SRAM_DTC and in SRAM_OC2. The fact that it happens with tightly-coupled memory is extremely baffling.
Any suggestions welcome.
Hi @expertsleepers ,
May I have the IDE version used with the board? I guess the board is an EVK board, right? Please kindly clarify.
Have a great day,
Kan
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MCUXpresso IDE v11.9.0 [Build 2144] [2024-01-05]
I'm not working with an EVK board - it's our production hardware design.
Hi @expertsleepers ,
Is it possible to share your code for a review? I will try to reproduce this issue here.
Have a great day,
Kan
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Hi @expertsleepers ,
Thanks for the information! but seems the code is for SPI peripheral access, may I understand this issue just happen in accessing external SPI memory? Did you test it on RT1060EVK or a custom board?
Please kindly clarify.
Have a great day,
Kan
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Correct, it's accessing an external flash memory via SPI, but this is irrelevant really - the problem seems to be that the data read from the LPSPI peripheral is not being stored in the processor memory unless I step through in the debugger.
I have not tried it on an EVK board.
Hi @expertsleepers ,
Thanks for the clarification! Maybe it is a timing issue, you know, core runs much faster than peripherals, so maybe there is some point you need to wait/check the rx fifo size, otherwise the code reads the fifo before the data is available.
Hope that makes sense,
Have a great day,
Kan
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