VGLite stride constraint (i.MXRT1176 GPU)

[svoulaz_ik]

Hello,

I am investigating the performance of LVGL on i.MXRT1176, mainly experimenting with benchmark sample (evkmimxrt1170_lvgl_demo_benchmark_cmX from SDK 2.14.0, LVGL 8.3.5). Overall, the performance is not exciting, especially on M4 core, but a preliminary analysis of the code shows that there is a certain margin for improvements. Among others, one thing that is not quite clear to me is the stride alignment constraint for bitmaps when using VGLite.

The demo is configured to use ARGB8888 pixel format - and of course VGLite acceleration. Sample bitmaps are 100x100 pixels, but bitmap rendering is not accelerated because the stride is not multiple of 16. Now, the VGLite API reference states (table 7) that for ARGB8888 the buffer and stride alignment should be 64, but the code checks for a stride alignment of 16. However, if the check on stride alignment is disabled, then apparently bitmap rendering by GPU works fine.

Which is the actual stride constraint for i.MXRT1176 GPU, if any?

Thanks!
Stefano

[Hui_Ma]

Hi,

First of all, sorry for the later reply.

Please refer <lv_gpu_nxp_vglite.h> of SDK provided lvgl_demo_benchmark_cmX projects, there with below defintion:

/** Stride in px required by VG-Lite HW. Don't change this. */
#define LV_GPU_NXP_VG_LITE_STRIDE_ALIGN_PX 16U

Wish it helps.

Mike

[svoulaz_ik]

Hello @Hui_Ma ,

thank you for the answer. I noticed that #define, which is somehow different from what stated in the documentation. 

From VGLite API Reference Manual Rev. 1.1 — 22 September 2022:

6.1 Pixel buffer alignment
To work correctly, VGLite hardware requires the data address and stride of a pixel buffer
to be aligned according to its pixel format. This requirement applies to all image formats.
The byte alignment requirement for a pixel depends on the specific pixel format. For
more details, see Table 7.
The pixel buffer start address alignment requirement also varies depending on whether
the buffer layout format is tiled or linear (vg_lite_buffer_layout_t enum):
• If the buffer layout is tiled (4x4 tiled), then the start address and stride must be 64 bytes
aligned
• If the buffer layout is linear, then the start address and stride must be aligned according
to the format of the pixel buffer, as described in Table 7

Now, the referred Table 7 reports an alignment of 32 for 16-bit formats and an alignment of 64 for 32 bit formats. This doesn't match the stride alignment in lv_gpu_nxp_vglite.h. However, the test on stride alignment is performed also in _check_source_aligned(), in vg_lite.c - and there it is consistent with the documentation.

However, referring to LVGL benchmark sources, it shall be noted that if [1] LV_GPU_NXP_VG_LITE_STRIDE_ALIGN_PX is set to 1 and [2] the test in _check_source_aligned() is bypassed (by just returning VG_LITE_SUCCESS), then any bitmap is correctly rendered by the lv_vglite_blit() call. This is the case for the images used in the LVGL benchmark, whose size is 100x100 (that is, stride not naturally aligned to 16 nor 32 nor 64).

It actually looks like no stride alignment is required for pixel buffers (at least, for linear layout). This would be a dramatic improvement, since any bitmap rendering would then be accelerated in hardware - not only bitmaps with aligned stride (which is a very strict and limiting constraint). The fallback to lv_draw_sw_img_decoded() makes image rendering extremely slow.

Can you please verify and confirm stride alignment constraint for source pixel buffer used by 2D GPU in i.MXRT1176?

Thank you in advance and best regards,
Stefano

[Hui_Ma]

Hi,

First of all, sorry for the later reply.

Please refer below info about Pixel buffer APIs:

Pixel Cache
− Imaging Engine (IM) inclu d es 2 fully associative caches
− 8 lines in each cache
− 64 bytes for each line
− For all formats, each pixel will be padded to 32 bits to fill the cache line
− One cache line can hold 4x4 pixel Tile or 16x1 pixel row

Pixel Buffer layout
− Tile mode vs. Linear mode

Source Image Alignment Requirement
− No pixel alignment requirement for width
− Byte alignment requirement depends on the specific format

Destination Alignment Requirement
− 4x4 Tile should be 64 B yte alignment for all tiled (4x4) formats.
− 16x1 Linear no alignment requirements for linear buffer formats.
− Alignment may also be limited by the alignment requirements of backend modules such as DC (Display Controller).

For linear buffer formats, there with no stride alignment constraint.

Mike

[mklinux]

hello Ma,

what will happen or is there any identified errors if I  make LV_GPU_NXP_VG_LITE_STRIDE_ALIGN_PX set to 1 and disable _check_source_aligned(). 

[Hui_Ma]

Hello,

Could you help to create a new thread about updated question?

We are willing to provide support at new created thread.

Thanks for the understanding.

best regards,

Mike