Using larger NAND flash than on MIMXRT1170-EVKB

[VojtechBaranek]

Hi. I am working on a feasibility study for using RT1170 with NAND flash as a telemetry storage. On the evaluation board MIMXRT1170-EVKB there is MT29F2G08ABAGAH4 NAND flash with 2Gb of storage. There is an example in the SDK called evkbmimxrt1170_flash_component_nand_semc_cm7 which demonstrates working with the memory. This example is great and works perfectly.

Now our goal is use this MCU (specifically MIMXRT1176CVM8A) on a custom board with large NAND flash MT29F64G08AECABH1 with 64Gb split into 2 dies with 32Gb each, as this picture from the datasheet shows. For the time being in the asynchronous mode.

Can you please advise me on how to achieve that? How must the SDK example be modified to allow working with this memory?

Thank you in advance. Best regards Vojtech.

[Kan_Li]

Hi @VojtechBaranek ,

I am sorry, but only one CE# on RT1170 for nand flash, as well as the R/B# signal, so it is not possible to use MT29F64G08AECABH1 with 64Gb split into 2 dies with 32Gb each due to this hardware limitation. 

Hope that makes sense,

Have a great day,
Kan

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[VojtechBaranek]

Hi @Kan_Li, thank you for your quick response.

We are aware that this is not supported natively without effort, but we have an easy way around this. Instead of SEMC driving the CE# pins, we will drive them by GPIO pins, simply assert one CE# low, perform SEMC operations, and deassert pin. We will select only one die at a time.

For R/B# pins we will join them by AND gate chip (like 74AUP1G09GW). Since we want to use one die at a time, this will work smoothly. Each die can drive the pin as if it was connected directly.

Now what I need an advice on is how to correctly set up the example for SEMC controller to properly interact with this memory via IPCMD and AXI. Thank you.

Best regards Vojtech

[Kan_Li]

Hi @VojtechBaranek ,

Thanks for the clarification! I think your solution should be able to work theoretically, but I would recommend using some kind of chip to control the direction of the native CE# instead of using GPIOs to simulate the CE#, so that no need to change the configuration on SEMC, the IP itself always communicates with one nand device , while the application code knows and controls which nand device it is talking with. 

Have a great day,
Kan

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[VojtechBaranek]

Hi @Kan_Li ,

alright, I see your point. Let me put my request for support differently. Let's say I only want to use the die 1 with one LUN, and the second one totally unconnected and forgotten. The die 1 will be connected the same way as the NAND flash on DevKit, with CE# driven by SEMC via the same pin as in the example. So I am basically just replacing the 2 Gb NAND flash from DevKit with the 32 Gb half of the chip from the same family whose part number I mentioned previously.

Now, please, what are the steps I need to take in rewriting the example to work properly with this new NAND flash?

Thank you. Best regards Vojtech.

[Kan_Li]

Hi @VojtechBaranek ,

If so, I think you just need to update the memory size as below:

Have a great day,
Kan

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[VojtechBaranek]

Hi @Kan_Li ,

that makes sense for the fields you mentioned. But shouldn't also columnAddrBitNum be extended?

Best regards, Vojtech.

[Kan_Li]

Hi @VojtechBaranek ,

Yes, you are right! For the chip you selected, I think kSEMC_NandColum_13bit should be used for the columnAddrBitNum.

Have a great day,
Kan

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