Using IMXRT1172 LPSPI EDMA transfer API, DMA IRQ handler called before SPI transfer is done

[Mike_M3]

Hi,

I've been using the LPSPI EDMA transfer API from the SDK (2.16.100) on IMXRT1172 to read and write SPI data simultaneously (i.e. a TX+RX transfer on two DMA channels with two buffers of the same size).  Unfortunately, it appears that the EDMA callback is getting called before the transfer actually finishes.  In the callback, checking LPSPI's SR, FSR, and RSR shows that SPI thinks it's still busy even though DMA thinks it's complete.  I.e. MBF is still set and TXCOUNT is 1.

SR = 0x01000100 (MBF, WCF)

FSR TXCOUNT = 1, RXCOUNT = 0

RSR = 0x00000002 (RXEMPTY, !SOF)

Now, if I was only doing TX, this could somewhat make sense as the SPI peripheral could still be clocking out the last byte loaded from DMA.  So in that case the DMA peripheral would actually be finished loading the last byte from RAM into the SPI data TX register, but SPI still had work to do to send it out.

However, when doing TX and RX simultaneously, I would have expected that if TXCOUNT was 1, then so would RXCOUNT be.  I.e. the DMA shouldn't be complete with RX until all the TX data is clocked out because the last byte needs to be transferred by DMA into RAM from the SPI RX data register, and this would only happen on the last clock cycle of the transfer.

Is this actually a problem?

If so, is it with the SDK?  Or with the hardware IP?

I was hoping to be able to check LPSPI SR in the DMA callback to determine if there are any SPI errors.

Thanks,

-m

[mayliu1]

Hi @Mike_M3 ,

Thank you so much for your interest in our products and for using our community.

DMA completion and SPI bus completion are two different concepts.

The eDMA callback indicates that the DMA engine has completed moving the configured number of bytes between memory and the LPSPI FIFO/register path. It does not necessarily mean that the LPSPI bus state machine has already completed the last frame or returned to idle.

For LPSPI bus completion, please check SR[TCF] or wait for SR[MBF] to clear.

Wish it helps you

Best Regards

May

[Mike_M3]

Yes, but in a TX/RX transfer, I would have expected the TX_COUNT and RX_COUNT to both be zero when DMA completes.  I.e., it should be impossible for RX DMA to complete before the last SPI clock, because the SPI peripheral wouldn't have shifted the last bit of the data into the RX FIFO until then, and DMA would not be able to copy the last byte into RAM until the last bit is shifted into the RX FIFO.  So in that case, both TX and RX should be completed before the DMA completes.  If it was only a TX transfer then yes, DMA could complete before SPI does and TX_COUNT could still be 1.

Thanks,

-m