MCU: RT1021CAG4A; Timer: QTMR2; PWM: 50KHz
During the test, the duty cycle of 10% to 90% is sent. When setting the value of updateddutycycle to change the PWM output duty cycle, it is found that the PWM waveform transmitted one value at a time is normal, that is, the positive duty cycle increases and the negative duty cycle decreases. However, when transmitting an array containing 9 duty cycle values, the positive duty cycle changes normally while the negative duty cycle remains unchanged
Solved! Go to Solution.
I am very sorry for the delayed response , I have not been able to reproduce the behavior that you are showing , using latest SDK v 2.11 and my RT1020 Rev A0. In my side, duty cycle remains unchanged. I also prepared an array with respective duty cycles and increased the transfer size to 18 bytes.
However in your code I noted that you are using the same DMA channel for updating the low and high duty cycles and also , that one transfer is made after the other.
I can see that you are able to increase the high duty cycle, so I recommend you using 2 DMA channels per each compare loader register (CMPLD1 and CMPLD2) and trigger DMA transfers for both at the same time , see RT1050_DMA_example.c attached. This one was made by one of my colleagues in this thread for the RT1050
If you are still facing issues , I want to get to the bottom of this, could you share me your complete main.c file for review, and specify me your SDK version?
Best regards,
Diego.
I am very sorry for the delayed response , I have not been able to reproduce the behavior that you are showing , using latest SDK v 2.11 and my RT1020 Rev A0. In my side, duty cycle remains unchanged. I also prepared an array with respective duty cycles and increased the transfer size to 18 bytes.
However in your code I noted that you are using the same DMA channel for updating the low and high duty cycles and also , that one transfer is made after the other.
I can see that you are able to increase the high duty cycle, so I recommend you using 2 DMA channels per each compare loader register (CMPLD1 and CMPLD2) and trigger DMA transfers for both at the same time , see RT1050_DMA_example.c attached. This one was made by one of my colleagues in this thread for the RT1050
If you are still facing issues , I want to get to the bottom of this, could you share me your complete main.c file for review, and specify me your SDK version?
Best regards,
Diego.
Thanks, Solved my problem
Thanks for the detailed reply! I will try to replicate on my side and get back to you as soon as I can.
Diego.
I want to replicate the behavior you are reporting. It seems that the PWM frequency increases , correct? As negative duty cycle does not decrease while positive duty cycle does.
Could you share with me your project? or a representative code snippet that you used ? This to check your settings.
Also, are you using the qtmr_inputcapture_outputpwm_dma SDK example as a reference?
Many thanks for your patience,
Diego.