Re:

[john71]

I included in my project (for MIMXRT1160-EVK) emWin GUI.

I get this error:

MIMXRT1166_EVK_CM4.axf section `NonCacheable' will not fit in region `SRAM_DTC_cm4' MIMXRT1166_EVK_CM4 C/C++ Problem
region `SRAM_DTC_cm4' overflowed by 7299032 bytes MIMXRT1166_EVK_CM4 C/C++ Problem 

when I look at the code I see

#define APP_IMG_HEIGHT     1280
#define APP_IMG_WIDTH      720

AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_frameBuffer[2][APP_IMG_HEIGHT][APP_IMG_WIDTH], FRAME_BUFFER_ALIGN);

It's a huge amount of memory and can not fit into existent region.

What do I miss?

Actually it tries to put the buffer in

__attribute__((section("NonCacheable,\"aw\",%nobits @"))) static uint32_t s_frameBuffer[2][1280][720] __attribute__((aligned(64)))

And it's quite big

Memory region         Used Size   Region Size    %age Used
NCACHE_REGION: 0 GB           16 MB             0.00%

Why the compiler refers to SRAM_DTC_cm4 section?

[john71 · Accepted solution]

OK. I found it. It should be defined at Settings->MCU Linker->Managed Linker Script

[john71]

So, the final question is - why I can not allocate the data in the section?

__attribute__((section("NonCacheable,\"aw\",%nobits @"))) static uint32_t s_frameBuffer[2][1280][720] __attribute__((aligned(64)))

Why I get

MIMXRT1166_EVK_CM4.axf section `NonCacheable' will not fit in region `SRAM_DTC_cm4' MIMXRT1166_EVK_CM4 C/C++ Problem
region `SRAM_DTC_cm4' overflowed by 7299032 bytes MIMXRT1166_EVK_CM4 C/C++ Problem 

Well...I looked at the example project. The generated linker file looks like

/* BSS section for NCACHE_REGION */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_NCACHE_REGION = .) ;
*(NonCacheable)
*(.bss.$RAM2)
*(.bss.$NCACHE_REGION)
*(.bss.$RAM2.*)
*(.bss.$NCACHE_REGION.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_NCACHE_REGION = .) ;
} > NCACHE_REGION AT> NCACHE_REGION

My one

/* BSS section for SRAM_ITC_cm4 */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_SRAM_ITC_cm4 = .) ;
*(.bss.$RAM2)
*(.bss.$SRAM_ITC_cm4)
*(.bss.$RAM2.*)
*(.bss.$SRAM_ITC_cm4.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_SRAM_ITC_cm4 = .) ;
} > SRAM_ITC_cm4 AT> SRAM_ITC_cm4

Where in the code I tie NonCacheable to NCACHE_REGION ?