RT1176 non-XIP eMMC to SEMC DCD configuration with 2x64MB SDRAM in parallel x32, shared CS0

[sykim2]

Hello,

I have a question regarding the DCD configuration for RT1176.

I am currently using a non-XIP configuration and plan to boot from eMMC and run from SDRAM (SEMC).

On the EVKB, SDRAM (SEMC) is configured as two 32MB SDRAM devices in parallel, for a total of 64MB memory.

I would like to keep the same circuit concept, but change the SDRAM to two 64MB devices in parallel (x32, shared CS0) so that the total memory size becomes 128MB.

However, when I modify only the DCD settings below, generate a Bootable Image, and download it, the system does not boot/work correctly.

DCD settings I modified
1) BR0 setting
400D_4010h = 0x8000001F

CS0 shared/parallel usage

Start Address: 0x8000_0000 ~

Memory Size: 128MB

Valid: 1 (The memory is valid and can be accessed)

2) SDRAMCR0 setting
400D_4040h = 0x00000E32

CAS Latency: 3

Column address bit number: 10 (COL field = 10b)

Column 8 Selection: 0b (determined by COL field)

Burst Length: 8 (011b)

Port Size: 32-bit

3) Additional change (DQS4 SION)
In the EVK default DCD, the SION setting for DQS4 was 0, so I changed it to 1 as below:

400E_8100h = 0x00000010

What works (single SDRAM case)
If I use only a single 64MB SDRAM device (not parallel), the system works correctly with the following setting:

400D_4040h = 0x00000E31

CAS Latency: 3

Column address bit number: 10

Burst Length: 8

Port Size: 16-bit

So, single 64MB SDRAM (x16) operation has been verified to work properly.

My questions
Could there be something incorrect or missing in my settings?

 

Thank you.

[Kan_Li]

Hi @sykim2 ,

I have tested your DCD changes with the sdk demo of evkbmimxrt1170_elcdif_rgb_cm7 on RT1170EVKB, but no issue happened, would you please specify how you verify the above changes?

Thanks for your patience!

Have a great day,
Kan

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[sykim2]

Hi Kan,

Thank you for your kind response.

I wasn’t sure which verification procedure you wanted me to describe, so I’m sharing the exact steps I followed:

1. H/W change (SDRAM part change)

- I already attached the photo in my previous post.

- I used Winbond W989D6DBGX6I based on the datasheet attached.

- The hardware was configured to use two x16 SDRAM devices in parallel (to make a 32-bit bus).

2. DCD bin file modification

- In the DCD bin file, I changed:

a. SDRAM size to 128 MBytes, and

b. Column address bit number to 10 bits.

3. Build “hello world” example

- I built the hello world example.

-  Since this is non-XIP booting, I configured it as an SDRAM boot.

-  I attached the memory layout/structure file as well.

4. Set DCD configuration using MCU Boot Utility

-  In MCU Boot Utility, I set the DCD configuration to SDRAM, so that it refers to the DCD bin file I attached previously.

5. Generate and download bootable image using MCU Boot Utility

- I generated a bootable image and downloaded it to the board via MCU Boot Utility.

With the above procedure:

- It works when dcd.bin is configured as 16-bit / 64 MBytes.

- It does not work when dcd.bin is configured as 32-bit / 128 MBytes.

Thanks again, and I would appreciate any guidance on what I should check next.

Best regards,

[Kan_Li]

Hi @sykim2 ,

Did you define SKIP_SEMC_INIT to avoid configuring SEMC again when the code was running on SDRAM? 

Have a great day,
Kan

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Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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[sykim2]

@Kan_Li 

Thank you for your advice.

However, the issue still remains and I am still seeing the same behavior.

Would you happen to have any additional reference materials or example projects that I could refer to?

Best regards,