RT1172 with external SDRAM via SEMC interface

[AndreiZi]

Hello,

I have an external SDRAM (AS4C16M16SA from Alliance datasheet is attached) connected to SEMC interface of MCU.

I use the SDK example semc_cm7.

The configurations are set in function SDRAM_InitSEMC();

As far as I understand here the parameters:

static status_t SDRAM_InitSEMC(void)

{

semc_config_t config;

semc_sdram_config_t sdramconfig;

uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

/* Initializes the MAC configure structure to zero. */

memset(&config, 0, sizeof(semc_config_t));

memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));

/* Initialize SEMC. */

SEMC_GetDefaultConfig(&config);

config.dqsMode = kSEMC_Loopbackinternal; /* For more accurate timing. */

SEMC_Init(SEMC, &config);

/* Configure SDRAM. */

sdramconfig.csxPinMux = kSEMC_MUXCSX0; // TODO understand what is this ???

sdramconfig.address = EXAMPLE_SEMC_START_ADDRESS;

sdramconfig.memsize_kbytes = 32 * 1024; /* 32 MByte = 4 M Words * 16 Bit * 4 Banks */

sdramconfig.portSize = kSEMC_PortSize16Bit; /* one 16-bit SDRAM port size*/

sdramconfig.burstLen = kSEMC_Sdram_BurstLen8;

sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit; // TODO

sdramconfig.casLatency = kSEMC_LatencyThree; // 2-3 TODO

sdramconfig.tPrecharge2Act_Ns = 21; /* tRP 18ns - 21ns : Pre-charge to refresh/row activate command (same bank) */

sdramconfig.tAct2ReadWrite_Ns = 21; /* tRCD 18ns - 21ns : RAS# to CAS# delay (same bank) */

sdramconfig.tRefreshRecovery_Ns = 70; /* Use the maximum of the (tRFC , tXSR). */

sdramconfig.tWriteRecovery_Ns = 14; /* tWR 12ns - 14ns : Write recovery time */

sdramconfig.tCkeOff_Ns = 42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/

sdramconfig.tAct2Prechage_Ns = 42; /* tRAS 42ns */

sdramconfig.tSelfRefRecovery_Ns = 70; // TODO from here down all the lines

sdramconfig.tRefresh2Refresh_Ns = 60;

sdramconfig.tAct2Act_Ns = 10; /* tRC/tRDD 10ns */

sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);

sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */

sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;

sdramconfig.refreshBurstLen = 1;

sdramconfig.delayChain = 6; /* For all temperatures. */

sdramconfig.autofreshTimes = 8; /* An additional eight Auto Refresh cycles (CBR) are also required before or after

programming the Mode Register to ensure proper subsequent operation. */

return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);

}

As I am a new in SDRAM I'll appreciate for some brief explanations on all the fields.

Few things are unclear:

1. sdramconfig.portSize - how I decide which one is to set?

2. sdramconfig.burstLen - what are consideration to choose one? pluses and minuses?

3. sdramconfig.casLatency - the same question

4. sdramconfig.refreshPeriod_nsPerRow - how to define?

5. sdramconfig.tPrescalePeriod_Ns - how to calculate?

How do I set the SDRAM clock frequency? In SDK example it comes from CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);

How I set it for my custom SDRAM?

In

Appreciate your support.

Andrei

[Omar_Anguiano]

Hello.
I will help you clarify how to chose the right parameter for you device, some of these parameters depend on the SDRAM datasheet while other there are some calculations to make.

1.Portsize, it refers to the data bus size of the memory. Your device is 16bit but you can use two SDRAM for 32bit port size(refer to the EVK).

2. The higher the burst higher performance as more data is transferred however it is needed to consider the refresh commands.

3. It depends on the device, higher performance when latency is low. The value will depend on your programed CAS latency of your memory.

4 and 5. Please refer to his example:

Best regards,
Omar

[Littell]

What document is this example taken from?  It implies there's a step-by-step initialization example that can be used as a template to identify the calculations needed to support a particular SDRAM device and create a correct DCD.

[diego_charles]

Hi @Littell 

We apologize for the delayed response, my colleague is currently out of the office, and I want to keep the follow up. 

I do not have the material related to the example he is showing, as it might be material that it is not officially released/stored on nxp.com, for example custom hands-on trainings to customers.

Could you help me to create another thread to keep a cleaner follow up? Per my understanding , you need step by step guide to enable SDRAM, ( calculations and DCD) during boot time. It is possible that you share with us the SDRAM part number that you want to use? Along its features? In the new thread. We may not have additional information on this, but we can adapt to your use case scenario, or have already something for your SDRAM model.

We appreciate your interest in our products, thank you.

Diego

[AndreiZi]

Hi Diego,

I also have a difficulties to make a proper DCD and/or use it correctly. My device is based on NAND flash memory connected by FlexSPI1 and external SDRAM (AS4C16M16SA-7BCN) connected by SEMC interface. Although I am able to configure it properly during the code and make it work properly I cannot configure it run as a main RAM in system and use during the boot to copy image from flash to external SDRAM and run from it.  

Hope you can give me a hand with this issue too.

Kind regards,

Andrei

[diego_charles]

Hi @AndreiZi 

I am sorry for the delayed response, I manually subscribed to the ticket to get updates, but I did not catch them.

Have you tried quiclkly testing the SEMC SDRAM XMCD using our Secure Provisioning Tool? There are 3 paramters that we can edit. 

Thank you for your patience. 

Diego

[AndreiZi]

Hi Diego,

Thank you for your response. Actually I already figured out this option and it works with some limitation of size. I cannot even build application with size more than ~1Mbytes. See attached print screen.

So it worked with code:

BOARD_SDRAM:      860864 B     32704 KB      2.57%

BOARD_SDRAM:     1052864 B     32704 KB      3.14%

And stopped to work with code size:

BOARD_SDRAM:     1628840 B     32704 KB      4.86%

BOARD_SDRAM:     1244864 B     32704 KB      3.72%

BOARD_SDRAM:     1148864 B     32704 KB      3.43%

The error message I see it before I am able to press button Build Image:

ERROR: Image size 0x001147B8 is greater than region available for the following image copies:

- image copy #0 starting at block index 2, size 0x00100000

Status of the operation: Failure: Operation `Build image` failed with an error: There are problems in settings, see Log for details.

Seems it somehow connected to the 0x100000 code size.

Please advise me with this issue.

Thank you in advance.

Kind regards,

Andrei Zinenko

[Omar_Anguiano]

Hello!

It seems that the error is set as the linker thinks that the image from NAND will be copied to internal RAM. Please rearenge the linker so the image is set to be copied directly to SDRAM. 

Solved: NAND FLASH XIP and boot modes - NXP Community

Best regards,
Omar

[Littell]

Hello?

[AndreiZi]

1.  It always write to defined address + size of 1 data offset. I.e. If I try to write to address
#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
It will write to (I see it in debugger memory window and later in read buffer) 0x80000002U address in case of data size of uint16_t.
2. Each 16th write access fails, and I see as a result or Zero or some garbage, see attached read buffer signed with red

[AndreiZi]

Thank you for your response. Unfortunately, I am in vacation until end of September. I will check your suggest when I come back.

I did not see how to configure the SDRAM clock speed. My memory is 143MHz if I remember correctly. SO original example from SDK is too fast? 

And why it writes data in memory with offset of 2 bytes?

Kind regards,

Andrei

[Omar_Anguiano · Accepted solution]

SEMC clock can be ajdusted with config tools so it matches your devices speed. 

SEMC access address with this scheme:

Best regards,
Omar

[AndreiZi]

Thank you for your help