status_t FRAM_read(uint32_t address, uint32_t* buffer, uint32_t size)
{
status_t status = kStatus_Success;
uint32_t addr_low = address & 0xff;
uint32_t addr_high = address >> 8;
uint32_t transfer_size = size;
uint32_t* transfer_buffer = buffer;
/* Check that LPSPI is not busy. */
if((LPSPI_GetStatusFlags(LPSPI1) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U)
{
return kStatus_LPSPI_Busy;
}
/* flush fifo. clear status flag. */
LPSPI_FlushFifo(LPSPI1, true, true);
LPSPI_ClearStatusFlags(LPSPI1, (uint32_t)kLPSPI_AllStatusFlag);
PRINTF("1 SR:%x, TCR:%x\r\n", LPSPI1->SR, LPSPI1->TCR);
/* start transfer.PCS is assered and RXMASK is de-assered. */
LPSPI1->TCR |= LPSPI_TCR_CONT(true)|LPSPI_TCR_CONTC(true)|LPSPI_TCR_RXMSK(true);
/*TCR is also shared the FIFO, so wait for TCR written.*/
if (!LPSPI_WaitTxFifoEmpty(LPSPI1))
{
return kStatus_LPSPI_Timeout;
}
PRINTF("2 SR:%x, TCR:%x\r\n", LPSPI1->SR, LPSPI1->TCR);
/* send read opcode and RXMASK is de-assered to start recieve data. */
LPSPI_WriteData(LPSPI1, READ_OPCODE);
LPSPI_WriteData(LPSPI1, addr_high);
LPSPI_WriteData(LPSPI1, addr_low);
LPSPI1->TCR &= (uint32_t)~LPSPI_TCR_RXMSK_MASK;
if (!LPSPI_WaitTxFifoEmpty(LPSPI1))
{
return kStatus_LPSPI_Timeout;
}
PRINTF("3 SR:%x, TCR:%x\r\n", LPSPI1->SR, LPSPI1->TCR);
while(transfer_size > 0)
{
LPSPI_WriteData(LPSPI1, (uint32_t)0);
if((LPSPI_GetStatusFlags(LPSPI1) & (uint32_t)kLPSPI_RxDataReadyFlag) != 0U)
{
*transfer_buffer = LPSPI_ReadData(LPSPI1);
//PRINTF("recieve data %d:%x\r\n", (size-transfer_size), *transfer_buffer);
transfer_size--;
transfer_buffer++;
}
}
LPSPI1->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK);
if (!LPSPI_WaitTxFifoEmpty(LPSPI1))
{
return kStatus_LPSPI_Timeout;
}
PRINTF("4 SR:%x, TCR:%x\r\n", LPSPI1->SR, LPSPI1->TCR);
return status;
}