RT1052: Why is it not possible to access a QSPI flash device as a memory store while XiP from another QSPI flash device on the same bus different chip-select?

[hasan_syed5]

Question

According to a couple of posts in the NXP community (referenced with links below) when running code out of QSPI Flash there seems to be a limitation that prevents general purpose storage actions on another QSPI Flash or storage device on the same bus managed by a different chip-select.

1. What is the reason for this limitation?
2. Are there plans on lifting this limitation?

References

- RT1050 QSPI Flash Limitations: https://community.nxp.com/thread/464926

- System hangs with simultaneous QSPI file access and XiP execution: https://community.nxp.com/message/1136406?commentID=1136406#comment-1136406

Background

Using the RT1052, I am trying to have XiP execution from QSPI Flash on A1 and access a different QSPI Flash on A2 for storage purposes (ie. read/write/erase to QSPI Flash on A2 while XiP from QSPI Flash on A1).

Best Regards,

Syed Jaffar

[jeremyzhou]

Hi SYED JAFFAR,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Q1) What is the reason for this limitation?
-- The data I/O lines doesn't transfer two different memory command simultaneously, which is determined by the QSPI protocol
 Q2) Are there plans on lifting this limitation?
-- Currently, there's no plan.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[hasan_syed5]

Thank you for the response jeremyzhou. 

Follow-Up Questions

There are still somethings that are unclear to me in your response and in some of the posts I have been reading. When you say...

"-- The data I/O lines doesn't transfer two different memory command simultaneously, which is determined by the QSPI protocol"

• Do you mean that there is a limitation in the FlexSPI controller itself or the limitation is in the QSPI Flash device hanging off the bus? 

• For instance, if I were to replace the QSPI Flash with a different part that supports XiP and RWW (Read While Write) operations, would I still be unable to XiP from a QSPI Flash on A1 and perform storage operations on a QSPI Flash on A2?

Some References I Used

• NXP Community Post

   Using QSPI Flash on imxrt1060 EVK for booting and back-up storage 

• White Paper (Memory Expansion with Adesto EcoXIP and i.MX RT)

        CROSSOVER TO MEMORY EXPANSION WITH ADESTO ECOXiP AND NXP’S i.MX RT CROSSOVER                           PROCESSORS: https://www.nxp.com/docs/en/white-paper/NXPADESTOWP.pdf

• On the post (link given above) a reference was given to a white paper from NXP (link above). If i understood correctly, they indicate that if you have a serial flash device which supports XiP and RWW operations, you could perform:

"... read operations from one bank while the device is busy programming or erasing another bank"

• Quote from the White Paper:

"Beyond addressing the performance of eXecute in Place operation, there are other unique features in EcoXiP to support application use cases. EcoXiP’s concurrent read-write, also known as read-while-write or RWW, allows the host processor to continue reading from a partition of the flash memory array while modifying data on another part. As an example, periodic logging of data which involves erase and program operations to the serial flash does not put the XiP program on hold. With the RWW feature, instruction and data fetching during programming continues as usual in a different partition of the flash. This scheme allows read operations from one bank while the device is busy programming or erasing another bank. The serial flash device can be configured into two banks: Bank A and Bank B. The border between the banks can be set with a granularity of 1/8th of the full flash array size. Read commands to one bank can be done while a write is in progress in the other bank.”

Thank you.

Regards,

Syed

[jeremyzhou]

Hi SYED JAFFAR,

Thanks for your reply.
1) Do you mean that there is a limitation in the FlexSPI controller itself or the limitation is in the QSPI Flash device hanging off the bus?
-- It's the limitation of the QSPI flash.
Q1)For instance, if I were to replace the QSPI Flash with a different part that supports XiP and RWW (Read While Write) operations, would I still be unable to XiP from a QSPI Flash on A1 and perform storage operations on a QSPI Flash on A2?
-- According to to the datasheet, Read While Write features seem to support write and read operation simultaneously, however, you'd better confirm it with the Adesto engineer.

Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------