RT1052 ADC function in low power run mode

[ffloree]

Hi,

I run into an issue of the ADC which doesn't work in low power run mode (all PLLs are disabled except for PLL2 bypass 24M XTALOSC, core runs at 24MHz frequency), but it's fine in full speed mode. I thought some settings of ADC clock might be incorrect. Having tried different clock sources (ADACK and IPG(12M)), ADC High Speed Configuration(ADHSC) isn't enabled and ADC1/2 clock gates are enabled, no any improvement. Is ADC able to work in low power run mode? If so, what else I can try? Thank you!

Case 1, use default settings (ADACK clock), it works in full speed run mode, but not low power run mode.

ADC_GetDefaultConfig(&adcConfigStrcut);
ADC_Init(ADC_BASE, &adcConfigStrcut);

Case 2, use 12MHz IPG clock, only tried in low power run mode, it doesn't work.

ADC_GetDefaultConfig(&adcConfigStrcut);
adcConfigStrcut.enableAsynchronousClockOutput = false;
adcConfigStrcut.clockSource = kADC_ClockSourceIPG;
ADC_Init(ADC_BASE, &adcConfigStrcut);

[ffloree]

Hi nxf46115‌

I found the cause. While entering low power run code, the analog bandgap reference circuitry would be powered down by setting bit REFTOP_PWD.

See SDK code LPM_LowPowerRun()->BandgapOff(). Can I keep this bit 0 and ADC available in low power run mode? Noticing the message below, I concern the power mode switching issues if a wrong setting of bit here, my system needs MCU to work in full speed run and low power run mode. Do you have any suggestion of making ADC usable in both low power run and full speed run modes?

[FelipeGarcia · Accepted solution]

Hi Tom,

There should not be an issue with that. As you can see in the application note I mentioned, Low Power Bandgap is disabled only in SNVS mode and Normal Bandgap is disabled in Low Power Idle, Suspend and SNVS mode.

Best regards,

Felipe

[ffloree]

Thanks nxf46115‌!

[FelipeGarcia]

Hello Tom,

I recommend you to check How to use i.MX RT Low Power Feature application note. In Low power run mode, all PLL are powered down.

If you use IPG CLK ADC should be able to work in Low Power run mode, please make sure you enable low power configuration in ADC_CFG[ADLPC] register.

Best regards,

Felipe

[ffloree]

Hi Felipe,

Thank you for looking at it.

The low power run mode has been working fine, the problem is only that ADC failed to work in this mode. By enabling ADLPC, still no any improvement, ADCx_GS is the same as before, reporting CALF(Calibration Failed Flag), but the hardware trigger isn't selected, no any ADC register setting, and stop mode has never been entered. The internal clock of ADC (ADACK) is dedicated whatever is in full speed run mode or low power run mode, I don't understand why the same ADC settings (or add ADLPC) doesn't work in low power run mode. By the way, its long sample mode (ADLSMP) was tried, not working either.