RT1051 randomly resets while changing clock frequency

[felek]

Hello all,

We are developing a system using the RT1051 microcontroller. This system has external SDRAM and eMMC memory. To reduce power consumption we're changing the CPU frequency between 4 and 528MHz (we have a few steps 4, 12, 24, 66, 132, 264, 528MHz) and we enable/disable PLL2 and PLL3.
Sadly we have random resets, but resets are very rare like once per a few days. The reason code for the resets is SRC_SRSR_IPP_RESET_B_SHIFT. After an investigation, we suspect that the switching source and clock speed of the SEMC can reset the system.

Run sequence:
- run our bootloader and init the SDRAM, SEMC_ROOT_CLK = 163,86 MHz from PLL2_PFD2
- the bootloader loads the main application image to the SDRAM
- run the main application
- If the CPU frequency is higher than 24 MHz the system uses external OSC and the SEMC uses PLL2_PDF2 (pic 1). When the CPU is 24 MHz or less then disable PLLs and switch to the internal OSC (reduce power). So in this case the SEMC uses PERIPH_CLK as the source (pic 2).

We tried to find any information in examples from NXP that switches source and clock for SEMC when the application is running but unsuccessfully.
Can we switch the source and clock speed of SEMC when the application is running?

[Miguel04]

Hi @felek 

Are you trying to only change the clock frequency? Is there an specific frequency value that causes the reset?

I recommend you to use the low power mode features of the RT1051.

• You can find an example on the SDK evkbimxrt1050_power_mode_switch_bm
•  AN12085 How to use i.MX RT Low Power feature
• AN12094 Power Consumption and Measurement of i.MXRT1050

Best Regards, Miguel.

[felek]

Hello @Miguel04 

Thanks for your reply.

We aren't sure but probably it is related to CPU frequency at 4MHz (when the system decreases to 4MHz or increases from 4MHz).

Our implementation is based on the document AN12085 and we use Low Power Run, but there is no information about changing the SEMC clock for external SDRAM. 

However, to reduce power consumption we switch to internal OSC and decrease the CPU speed to 4MHz. This solution was allowed in the MCUXpresso Config Tools (I mean change clocks without any warnings).

Additionally, when the system decreases CPU frequency <24MHz we switch the SEMC to PERIPH_CLK. Do you think it can be harmful to the system's stability?

[Miguel04]

Hi @felek 

It is not recommended to change the clock frquency or source of the SEMC during run mode, look into chapter 5.3.3 How to change clock source for SPI Flash and SDRAM from AN12085.

Also, the reset could be caused by: during low power mode, a perihperal that do not work on this state, can you confirm if this is the case on your project? Which pripherals are you using?

Best Regards, Miguel.

[felek]

Hi @Miguel04 

You're right about changing SEMC during run mode. We use LPSPI, SEMC, LPUART, USDHC, LPI2C.

However, after additional tests, we discovered that the SEMC probably isn't the source of the issues.
After disabling a bandgap and a weak LDO there aren't resets.
A few devices worked without any resets for a few days.
Sadly, this change causes more power consumption and is inconsistent with the AN12085 document.