Missing Register Definitions for SRTC

[andrewkinmont]

Hello,

We are planning on using the SRTC timer as a means of bringing the i.MX RT1064 processor in our application out of SNVS mode. When we look in the Reference Manual, there seems to be some definitions missing for the critical registers.

In particular, the LPSRTCMR and LPSRTCLR registers are referenced in the text (see section 19.4.1.3), but there are no definitions for these registers. Further, bit 0 in the LPCR register appears to be the SRTC enable bit, and bit1 in the same register appears to be the time alarm interrupt enable, but these are both listed as reserved in the Reference Manual.

There are details in the drivers in the SDK, just nothing in the Reference Manual.

Is this just a documentation issue (accidental omission from the Reference Manual), or is there a plan to remove the SRTC timer from the i.MX RT1064 in a future release of the silicon?

Thanks and best regards,

Andrew

[jingpan]

Hi Andrew,

yes, it is a bit strange that these two register is not list in SNVS memory map. They are security related register but there function is not special. You can see them in RT1050SRM. They will not be removed. It is just a document issue.

Regards,

Jing

[andrewkinmont]

Thanks, Jing.

I now have the manual, so all is now clear.

Regards,

Andrew