MIMXRT1175DVMAA, LPSPI clock duty cycle is not 50%

[TCL_1]

Hello,

On my custom board based on MIMXRT1175DVMAA, I use the LPSPI_4 as host to communication with a SPI EEPROM. But I found that the SPI serial clock duty cycle is not around 50%, whatever in mode 0 or mode 3 (see following waveform). In condition of operating frequency less than 5Mhz, it also violated the clock high/low duration requirement of EEPROM, due to the asymmetrical clock waveform.

My questions are:

1. Is it normal for the MIMXRT1175DVMAA LPSPI controller to generate asymmetric clock waveforms?

2. Is there a method to adjust the duty cycle of LPSPI clock? then the SPI bus can meet chip's Timing requirements without decrease operating frequency.

Thanks!

Tyrone

[jingpan · Accepted solution]

Hi @TCL_1 ,

This is because CCR[SCKDIV] is set an odd number.

I tried to set it to an even number, then its duty come back to 50%.

Regards,

Jing