MIMXRT 117x SPI Slave Rx FIFO Overrun Issue.

[imxrt1062_1172_user]

Hello, we use MIMXRT1062 as SPI Master and MIMXRT1176 as SPI Slave on our Products. We find a strange issue on the SPI Slave. We have frame size of 9Words and the RxWatermark is always set 8Words. When we just send 1 Message with above frame size we find the Receive Error Interrupt happening straight away. The RxFIFO size is 16 Words so why would the overflow happen? 

[Gavin_Jia]

Hi @imxrt1062_1172_user ,

Thanks for your questions and info!

The watermark is set to trigger an interrupt or DMA to process the data in the FIFO when the watermark is reached. It is to prevent FIFO overflow and provide flexibility. When your watermark is 8 words and the frame size is 9 words, please make sure that the data is processed in time in ISR to prevent overflow. The SDK example evkmimxrt1170_lpspi_interrupt_b2b_transfer_slave_cm7 is a good reference.

Best regards,
Gavin