Hi.
I am doing my job on board iMX RT1020EVK.
Just , I faced to Link error <<region `SRAM_DTC' overflowed by xxxxbytes>> message after merging example <<lwip_ip4_ip6_echo_freertos>> on example code <<freertos_flash_operation>>
after studying, I found solution from https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649, https://community.nxp.com/t5/i-MX-Processors/106axf-section-bss-will-not-fit-in-region-SRAM-DTC-regi...
anyway, I found somethings strange on avoiding problem by using SDRAM as first RAM index on example <<lwip_ip4_ip6_echo_freertos>>,
lwip example does not initialize SDRAM and has not routed pin map
It means that MCU does not recognize SDRAM, no Enable , no clock.... Right ??
How can it be possible using SDRAM on run-time in lwip_ip4_ip6_echo_freertos sdk exam. ??
(that example does not include driver. file. fsl_semc.c)
解決済! 解決策の投稿を見る。
Hi @Seongyon_Jeong ,
BOOT ROM can initialize SDRAM by reading the data in DCD. You can compile the DCD data into application by define XIP_BOOT_HEADER_DCD_ENABLE=1
The DCD data is in dcd.c. If your SDRAM is different with RT1020-EVK, you should modify it according to your SDRAM.
Regards,
Jing
Hi @Seongyon_Jeong ,
BOOT ROM can initialize SDRAM by reading the data in DCD. You can compile the DCD data into application by define XIP_BOOT_HEADER_DCD_ENABLE=1
The DCD data is in dcd.c. If your SDRAM is different with RT1020-EVK, you should modify it according to your SDRAM.
Regards,
Jing