Low latency connection of i.MXRT1176 to an FPGA

[simongornall]

I'm connecting a 1176 to an FPGA, which is in turn connected to another micro. The FPGA is behaving like memory to the other CPU, but actually passing any memory read/write requests onto the 1176 to serve, so that the 1176 can naturally "DMA" data into the memory space of the other CPU simply by memcpy().

The other CPU is a lot slower than the 1176. What is the fastest way to do the above that does not use the CM7 ? I've thought of a few possible ways:

• Use a 32-bit GPIO port and have the CM4 sit there either in a tight loop polling or being interrupt-driven by the fall of the other CPU's CLK line on its bus. Then the CM4 pulls data from the (shared with CM7) attached HyperRAM and pushes it out over another dedicated GPIO bus.
• Use FLEXIO - I'm not familiar with FLEXIO (and frankly, it looks fiendishly complicated) but it seems to be a way for the above to be slightly automated and data aggregated into a packet before being dispatched by the CM4/CM7. This grouping of data might be useful, since the data structure will probably be {command, data, data,...} as in {READ_MEM, Address, Range} or. {WRITE_MEM, address, data, data, ...}
• Set up the FPGA to respond as an SRAM - I'm not really in favour of this because I've already used most of the pins I'd need elsewhere The design uses HyperRAM so that I don't need the external memory controller and I get more GPIO, but it might be possible to move things around
• SPI doesn't really have the bandwidth I want, from a back-of-the-envelope calculation. It's roughly a 2MHz (but I'd like it to work faster than that) signalling rate, with address, command (read/write), and data to transfer in both directions.

The crucial thing is that the entire round trip [other CPU -> FPGA -> 1176 -> FPGA -> Other CPU] can only take ~300ns. The FPGA is relatively fast (a clock or two for sync, but the logic and pins are fast), so I'm primarily concerned with keeping the latency down for data coming into and leaving the 1176.

So, what's the lowest latency approach ?  

[Masmiseim]

Hello simingornall,

the flexSPI follower interface, which is introduced with iMXRT1180, could maybe meet your requirements.

Regards

[jingpan]

Hi ,

RT1180 will go to market in the end of this year.

Regards,

Jing

[jingpan]

Hi @simongornall ,

RT1176 hasn't any port which support accessing internal RAM directly. So M4/M7 core must involved to send data. 

Maybe you can let CPU put address and number in FPGA register/RAM, then send interrupt to RT1176. RT1176 then get the address and number from FPGA and send required data to FPGA again. At last, CPU read data from FPGA. I think the benefit is you needn't design special protocol and interface for it. And the speed is depend on the interface. SEMC SRAM is fine.

Regards,

Jing