Hello support team,
We are running evkmimxrt1170_lwip_ping_freertos_cm7 for 1Gb example on our custom board.
But we were facing a working problem and need your help.
First, I would like to describe my project:
- Custom board with eMMC (no Flash memory), no problem with board (almost peripheral working)
- Using 1Gb Ping example (modify pin map)
And, following the below guide from NXP to modify the NCache region:
board.c
enet_ethernetif_kinetis.c
But the ethernet 1Gb is still not working
Terminal log:
I was checked the build memory and it was shown as below:
Questions:
1. Does NCACHE_REGION belong to the SDRAM?
2. How can this problem be fixed to make the 1G Ethernet work?
Best regards,
Tu Cao
Hello @Gavin_Jia ,
Thank you for your response.
First, we are using eMMC as an external memory (remove flash memory). There is SDRAM used as intermediate memory.
In this Enet 1G demo, we are testing directly on the SDRAM (debugging) on the Ozone application.
After checking carefully with the NXP Ping demo, I found that there was a mistake in the MCU memory region.
The lwip_ping_freertos already has the NCACHE_REGION, and I don't need to arrange another memory region.
I re-setup the system as below:
- enet_ethernetif_kinetis.c
- Enable the "Link application to RAM"
- Change symbols to "0" because we are using external emmc memory:
After changing 3 things above, the terminal log has been shown below:
There is no receiving log "ping: recv 192.168.01100 3 ms"
Please guide me on how to fix it?
If there is any example source on this case, please help to share.
Best regard,
Jay Cao
Hi @JayCao ,
Thanks for your interest in NXP MIMXRT series!
In your custom board, it is not using SDRAM only emmc right? In that case you could have deleted the unused memory from the memory map, it doesn't matter.
In your operation, the general steps are right, but I guess it could be wrong in the MPU configuration. So my suggestion is to minimize your modifications and steps.
Step1: Delete unused memory. Divide a piece of memory out of OCRAM to be used as NCACHE (recommended to be the end of OCRAM);
Step2: add the description of the newly divided region in the extra link script;
Step3: modify the region configuration code in MPU;
Step4: directly manually customize the region where your variables are stored; you can refer to that original post or this thread: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/i-MX-RT-1020-using-SRAM-OC-and-ITC/m-p/1956514/e...
Best regards,
Gavin
