Issues when using SDRAM for general data storage on i.MXRT1176

[JonMcLeanSMC]

Hello,

I am currently trying to configure the RT1176 to use SDRAM (32MB) for general data/program storage however I am having some issues. Specifically the application stops executing/freezes during the ResetISR function. I have looked at other threads however am yet to find any solution.

I have the following predefined symbols:

I have used the following memory configuration:

Finally, I provided the following settings for the linker:

I am not sure about the heap/stack locations (followed another thread) however even changing those back to default (post data and end respectively) the issue still occurs. Furthermore I am not sure about the Heap being allocated to SDRAM_NCACHE_REGION however another thread suggested that the heap should be allocated to an non cacheable region.

Any help would be greatly appreciated. If you need anymore information I'd be happy to provide it

Thanks,
Jon

Note: Here is the debug flow when executing the application:

1) Initial Breakpoint at ResetISR

2) First Step Into after initial breakpoint

3) Next Step (throws 0xdeadbeee)

[jingpan]

Hi @JonMcLeanSMC ,

Please use this script file to initialize SDRAM before debug code.

Regards,

Jing

[JonMcLeanSMC]

Hi @jingpan ,

Thank you for the response, it proved to be very helpful. I've now set up the script so the SDRAM is initialized before debug however I am still having issues getting my program running.

Instead of failing inside of SystemInit() as before, it will now "fail" upon finishing executing that function (as shown below).

1) Step towards the end of SystemInit() (specifically the SystemInitHook() call)

2) Step Over SystemInitHook()

The memory configuration is still the same as the last post. Any ideas as to what the issue might be? Furthermore I've attached the modified version of your script that I used to initialize the SDRAM (as my board uses JLink/Freelink) in case I have made some stupid mistake.

Thanks,
Jon McLean

[jingpan]

Hi @JonMcLeanSMC ,

I made a running in SDRAM demo. It use CMSIS-DAP but jlink should be almost same. Please compare the .ld file.

Regards,

Jing

[JonMcLeanSMC]

Hi @jingpan,

I've updated my LD script to more closely match the one you've provided in your example. This has allowed the program to get past the SystemInit function that it was previously failing on. However now it is failing while copying data sections from flash to RAM. When it fails two active faults are shown, specifically BFARVALID(7) and PRECISERR(1). Additionally a FORCED(30) fault is shown.

Here is some screenshots of the fault/registers as well as the debug thread trace:

I presume the occurence of the faults indicates an issue with the setup of the SEMC however I've gone through and can't find any issues.

Let me know if you have any suggestions.

Thanks,

Jon McLean

Note: I've attached the updated LD script for reference.

[jingpan]

Hi @JonMcLeanSMC ,

Is you board a customer board or EVK? If it is your own board, can it pass the SEMC demo in SDK?

Regards,

Jing

[JonMcLeanSMC]

Hi @jingpan ,

It is an third party board (specifically a TQ development kit). After a little bit of modification it does pass the SEMC example. I have modified the SEMC initialization to be the following:

    /* Configure SDRAM. */
    sdramconfig.csxPinMux           = kSEMC_MUXCSX0;
    sdramconfig.address             = 0x80000000;
    sdramconfig.memsize_kbytes      = 32 * 1024;       			/* 32MB = 32*1024*1KBytes*/
    sdramconfig.portSize            = kSEMC_PortSize16Bit;		/*two 16-bit SDRAMs make up 32-bit portsize*/
    sdramconfig.burstLen            = kSEMC_Sdram_BurstLen8;
    sdramconfig.columnAddrBitNum    = kSEMC_SdramColunm_9bit;
    sdramconfig.casLatency          = kSEMC_LatencyThree;

    sdramconfig.tPrecharge2Act_Ns   = 18; 						/* tRP 18ns */
    sdramconfig.tAct2ReadWrite_Ns   = 18; 						/* tRCD !(ns */
    sdramconfig.tRefreshRecovery_Ns = 115; 						/* Use the maximum of the (trfc , txsr). */
    sdramconfig.tWriteRecovery_Ns   = 15;  						/* tWR !%ns */
    sdramconfig.tCkeOff_Ns =
        42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
    sdramconfig.tAct2Prechage_Ns       = 42; 					/* tRAS 40ns */
    sdramconfig.tSelfRefRecovery_Ns    = 115;                   /*Old 70ns;* tXSR*/
    sdramconfig.tRefresh2Refresh_Ns    = 60;                    /*Needs to meet tRFC/tRC timing*/
    sdramconfig.tAct2Act_Ns            = 60; 					/* tRC/tRDD 2ns */
    sdramconfig.tPrescalePeriod_Ns     = 160 * (1000000000 / clockFrq);
    sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
    sdramconfig.refreshUrgThreshold    = sdramconfig.refreshPeriod_nsPerRow;
    sdramconfig.refreshBurstLen        = 1;
    sdramconfig.delayChain             = 2;

Thanks,

Jon

[jingpan · Accepted solution]

Hi @JonMcLeanSMC ,

Add these modification to DCD. It will be fine.

Regards,

Jing