Hi,
I found some fusemap discrepancies in the manual:
Security Reference Manual for the i.MX RT102x Processor
IMXRT102XSRM
Rev. 0, 07/2020
#### Problem 1:
In tables 4-2 to 4-7, we have these settings:
0x470[1] L1 D-Cache DISABLE
0x470[20] Reserved
0x470[23] USDHC_CMD_OE_PRE_EN
0x470[30:24] MMC_DLL_DLY[6:0]
But in Table 4-9. Fusemap Descriptions, these are different:
0x470[1] BT_MPU_DISABLE
0x470[20] BT_LPB_POLARITY
0x470[23] Reserved
0x470[30:24] MMC_DLL_DLY[6:0] Setting field differs: "Conneted to LVDS module."
Which ones are correct please?
Similar problems seem to appear in manuals:
i.MX RT1020 Processor Reference Manual, Rev. 2, 01/2021
i.MX RT1050 Processor Reference Manual, Rev. 3, 8/2019
#### Problem 2:
In Table 4-9. Fusemap Descriptions, fuses 0x460[7:6] seem to be described twice:
0x460[6] Reserved
0x460[7] Reserved
0x460[7:6] FLASH_CONNECTION_SEL
Which ones are correct please?
Many thanks and kind regards,
Ronnie
Hi Ronnie,
I have received confirmation from internal team. Please check it below:
Thank you for bringing this to our attention.
Best regards,
Felipe
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Hi Felipe,
Thanks for your reply.
Regarding issue #1:
Unfortunately what you said about BT_MPU_DISABLE seems to contradict this posting: https://community.nxp.com/t5/i-MX-RT/RT1020-RT1050-ref-manual-issue-BT-MPU-DISABLE-and-L1-I-Cache/m-...
Also, I just want to confirm that all the settings in #1 are correct in table 4-9 (and incorrect in the other tables)?
Kind regards,
Ronnie
Hi Ronnie,
Sorry for the late reply, I have confirmed with my colleague and with internal team that the information from my previous reply is correct.
Best regards,
Felipe
Thank you.
Hi Ronnie,
Thank you for reporting this with us. I am going to check internally and I will update this thread when I receive confirmation about this.
Best regards,
Felipe