How many TDM channels can be supported in RT1170 SAI1 TX & RX

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How many TDM channels can be supported in RT1170 SAI1 TX & RX

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ZHOU_XIAO
NXP Employee
NXP Employee

Hello, all

 

According to RT1170 RM , RT1170 SAI1   support 4 TX & 4 RX data line.

Each data line support max 32 words (word size 8- to 32 bit) 

each 32-bit FIFO can pack 8 bit or 16 bit.

ZHOU_XIAO_1-1680745185477.png

 

And according  to AN12202,   8 FIFO(32 bit) can support 8 TDM channels . 

 

 

ZHOU_XIAO_0-1680744852133.png

 

Question   SAI1 maxisumly can support following TDM channels ?

 

Guess1 :

TX can support :  4 dataline × 32 ( FIFO numbers)=128 TDM chs

RX can support:  4 data line × 32 (FIFO numbers) =128 TDM chs

Guess2:

each  32 bit FIFO of RT1170 can only support 16 bit packing. 

TX can support :  4 dataline × 32 (FIFO numbers) /2 =64 TDM chs

RX can support:  4 data line × 32 (FIFO numbers)/2  =64 TDM chs

 

@kerryzhou  

Best regard

ZHOU

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @ZHOU_XIAO ,

   Thanks for your trust, in fact, we are colleagues!

    About your question, please note the following two points, then you will get the answer:

1. Please note, RT1170 SAI1 didn't support 4 TX & 4 RX data line in the same time, this is very important.

kerryzhou_0-1680750115758.png

kerryzhou_1-1680750173995.png

Because the SAI1_TX_DATA1-DATA3 share the line with SAI1_RX_DATA1-DATA3.

 

2. each data line can support up to 32 channel TDM, this is confirmed.

 

I think, you already get the answer.

BTW, to our NXP engineer, we have the internal community for discussion:

https://community.nxp.com/t5/RT-4-Digit-10xx-11xx-12xx/gh-p/52590

Then, our AE can also help us.

 

Wish it helps you!

Best Regards,

Kerry

 

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @ZHOU_XIAO ,

   Thanks for your trust, in fact, we are colleagues!

    About your question, please note the following two points, then you will get the answer:

1. Please note, RT1170 SAI1 didn't support 4 TX & 4 RX data line in the same time, this is very important.

kerryzhou_0-1680750115758.png

kerryzhou_1-1680750173995.png

Because the SAI1_TX_DATA1-DATA3 share the line with SAI1_RX_DATA1-DATA3.

 

2. each data line can support up to 32 channel TDM, this is confirmed.

 

I think, you already get the answer.

BTW, to our NXP engineer, we have the internal community for discussion:

https://community.nxp.com/t5/RT-4-Digit-10xx-11xx-12xx/gh-p/52590

Then, our AE can also help us.

 

Wish it helps you!

Best Regards,

Kerry

 

 

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ZHOU_XIAO
NXP Employee
NXP Employee

Hello, @kerryzhou  I have a additional question about this topic.

As the following equation shows, the number of chs also depends on the sample rate,

You said that . each data line can support up to 32 channel TDM, what is the sample rate in your case?

 

ZHOU_XIAO_0-1681361555315.png

 

Best regard

ZHOU

 

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @ZHOU_XIAO ,

  sample rate is determined by your application.

  You can use the sample rate, channel number, to calculate which bclk you needed, then configure the related MCLK and clock source frequency.

 

Wish it helps you!

Any new issues, welcome to create the new case.

Best Regards,

Kerry

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