Hardware Design Guide for MIMXRT1062DVN6B (NVCC_SPIX)

[bennxp]

Is there a hardware design guide for the MIMXRT1062DVN6B? (ie the 1060X series)? The latest I see is MIMXRT105060HDUG which doesn't mention the extra SPI0 and SPI1 banks in the 225-pin package. I'm looking to confirm if the NVCC_SPI0 and NVCC_SPI1 can be powered with 1.8Vor 3.3V like the NCC_SD0 / NVCC_SD1 banks. Also any information about recommended number / value of decoupling caps for those banks and power sequencing would be great as well.

Thanks,

[Gavin_Jia]

Hi @bennxp ,

Thanks for your interest in NXP MIMXRT series!

The official documentation does not provide a hardware development manual specific to the RT1060X. Regarding NVCC_SPIX, these are new, independent power domains that support either 1.8V or 3.3V. For the selection of decoupling capacitors, refer to NVCC_GPIO; please do not skimp on capacitors. There are no special requirements regarding power-up sequencing.

Best regards,
Gavin