FlexIO-based camera interface max PCLK frequency

[powerfeatherdev]

Hi, I'm currently looking into using the FlexIO-based camera interface example as a base for talking to another type of interface somewhat similar to it. That is, an interface where the device outputs a clock, and data access is synchronous to that clock.

On the reference manual, there is a "FlexIO Application Information Section"  which states some  limits for specific FlexIO interface implementations. For example, for the SPI Master, it says:

Due to synchronization delays, the setup time for the serial input data is 1.5 FlexIO clock cycles, so the maximum baud rate is divide by 4 of the FlexIO clock frequency.

However, for the Camera Interface, it does not state such thing. So does that mean that the the PCLK be theoretically as high as the FlexIO base clock (120 MHz)?

[EdwinHz]

Hi @powerfeatherdev,

That is correct, the maximum PCLK frequency is directly proportional to the maximum FlexIO peripheral clock.

BR,

Edwin. 

[powerfeatherdev]

I see, so it can get up to 120 Mhz? Is this something that has been tested by NXP? I would test this myself, but the EVK that I bought apparently does not expose enough FlexIO pins to test this (RT1010).

[EdwinHz]

Hi @powerfeatherdev,

This has not been properly tested by NXP, no. It is only the theoretical limit.

BR,
Edwin.

[powerfeatherdev]

Hi Edwin, up to what speed was NXP able to push this? I think I might need at least 60 MHz.

[EdwinHz]

Hi @powerfeatherdev,

The tested scenarios we have done are described on the following application note: Using FlexIO to emulate Parallel Camera Interface on i.MX RT.

BR,
Edwin.