FLEXSPI_Init(...) and hardfault(HardFault_Handler_Ram)

[Cindy]

Hi,

I have been trying to initialise QSPI (FLEXSPI-B) interface so that the processor can communicate to its slave.

However, executing the following line causes a hardfault(HardFault_Handler_Ram).

FLEXSPI_Init(FLEXSPI, &config);

FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortB1);

HardFault is triggered even I commented the code after FLEXSPI_Init(FLEXSPI, &config); . 

There are no signals being sent from FLEXSPI-B port. I am using the initialisation function from the SDK example - flexspi_not_polling_transfer.

The application software is executed from qspi nor flash for my project.

I have read  the following question, however, unable to apply the solution to my problem :-

https://community.nxp.com/t5/i-MX-RT/FLEXSPI-Init-mostly-FLEXSPI-SoftwareReset-causes-a-hardfault/m-...

I have initialise PIT and other timers, disabling global interrupts during initialisation will not solve the problem.

The code is executed from NOR Flash. The slave connected to FLEXSPI-B is FPGA.

Please advice next step. Your help would be very appreciated.

Thank you!

Best Regards,

Cindy

#####

My code:-

static flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 30000000,
.isSck2Enabled = false,

.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,

.CSHoldTime = 3,
.CSSetupTime = 3,
.dataValidTime = 0,
.columnspace = 0,
.enableWordAddress = 0,
.AWRSeqIndex = FPGA_CMD_LUT_SEQ_IDX_WRITE,
.AWRSeqNumber = 1,
.ARDSeqIndex = FPGA_CMD_LUT_SEQ_IDX_READ,
.ARDSeqNumber = 1,

.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,

.enableWriteMask = false
};

IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS, 1U);


const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};

CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 35);
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */

CLOCK_SetDiv(kCLOCK_FlexspiDiv, 7);

flexspi_config_t config;
/*Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);

/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableReadAddressOpt = true;
config.ahbConfig.enableAHBCachable = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
FLEXSPI_Init(FLEXSPI, &config);

/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortB1);

/* Update LUT table. */
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);

/* Do software reset. */
FLEXSPI_SoftwareReset(FLEXSPI);

[Cindy]

Hi Jay_Heng,

I think I know the root cause to the hardfault.

For my project, FLEXSPIA is connected to QSPI_NOR_FLASH (XIP), and, FLEXSPIB is connected to FPGA chip.

FLEXSPIA clock initialisation is done separately. I attempted to configure the clock differently for FLEXSPIB later on as I thought the clock source for FLEXSPIA and FLEXSPIB can be different. I think this reconfiguration of the FLEXSPI clock source caused the hardfault, both of the FLEXSPIA and FLEXSPIB shares the same clock source. However, please correct me if I am wrong.

Please confirm:-

a) FLEXSPIA and FLEXSPIB shares the same clock source.

    For example, if  FLEXSPIA clock  has been configured as shown below:-

         USB1 PLL(3) = 480MHz is selected

         PFD0_FRAC = 22

         FLEXSPI_PODF = /8

  FLEXSPIB should used the same clock configuration as FLEXSPIA(XIP).

Thank you.

Best Regards,

Cindy

[Cindy]

Hi Jay,

Thank you for getting back to me.

For your information, the following FLEXSPI-A lines are connected to NOR FLASH (XIP):-

FLEXSPI-A-DATA0
FLEXSPI-A-DATA1
FLEXSPI-A-DATA2
FLEXSPI-A-DATA3
FLEXSPI-A-SCLK
FLEXSPI-A-SS0-B

The problem I am having is FLEXSPI-B port initialisation:-
FLEXSPI-B-DATA0
FLEXSPI-B-DATA1
FLEXSPI-B-DATA2
FLEXSPI-B-DATA3
FLEXSPI-B-SCLK
FLEXSPI-B-SS0-B
FLEXSPI-B-DQS

My question is will  initialisation of FLEXSPI-B affects FLEXSPI-A (XIP)?

I look forward to your reply.

Thank you!

Kind Regards,

Cindy

[jay_heng]

What is your application code regarding FlexSPI module initialisation?Can you please share your source file?

[Cindy]

#include "fsl_flexspi.h"
#include "fsl_iomuxc.h"

#define FPGA_COMM_FLEXSPI FLEXSPI
#define FLASH_SIZE 0x2000
#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
#define FPGA_CMD_LUT_SEQ_IDX_READ 0U
#define FPGA_CMD_LUT_SEQ_IDX_WRITE 1U

static flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 25000000, // 25MHz (<30MHz)
//.isSck2Enabled = false,

.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,

.CSHoldTime = 3,
.CSSetupTime = 3,
.dataValidTime = 0,
.columnspace = 0,
.enableWordAddress = 0,
.AWRSeqIndex = FPGA_CMD_LUT_SEQ_IDX_WRITE,
.AWRSeqNumber = 1,
.ARDSeqIndex = FPGA_CMD_LUT_SEQ_IDX_READ,
.ARDSeqNumber = 1,

.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,

//.enableWriteMask = false
};

#define CUSTOM_LUT_LENGTH 64
const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {

/* Read Data: control byte = 0 (Read), */
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x0, kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x18), // 0x0: control byte - read, 0x18 -> 3 byte address, 3*8 = 24 bits
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x4, kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x4), // 0x4(1) = 4 dummy cylces, 0x4(2): 4 bytes read out
0, 0, /* NOTE: initialise this way to avoid "sorry, unimplemented: non-trivial designated initializers not supported" */

/* Write Data: control byte = 0 (Read), */
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
0, 0, 0,
};


void initialise()
{
// ************************ initialise pins ************************
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B,
1U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS,
1U);

// ************************ initialise clock ************************
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
/*
* USB1 PLL: 480Mhz
* PLL3_PFD0: 664.61Mhz (/13 * 18)
* FLEXSPI_PODF: 2 (to get 332.3Mhz) */
// CSCMR1[FLEXSPI_PODF]
// 14.7.7 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)
// Figure 14-2. Clock Tree - Part 1: IMXRT1050RM

// USB1 PLL ((480MHz PLL3) => ((480MHz * 18) / fraction)
// PFD0_FRAC = 24
// 480*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock TO 360MHZ. */

// CCM_CSCMR1 field(bit 30-29) descriptions
// FLEXSPI_CLK_SEL
// 00 derive clock from semc_clk_root_pre
// 01 derive clock from pll3_sw_clk
// 10 derive clock from PLL2 PFD2
// 11 derive clock from PLL3 PFD0
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */

//
// FLEXSPI_PODF = 3 bit (0..7)
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 7); /* Divide the clock by 3 to get flexspi root clock 360MHZ / 3 = 120MHZ */

// ************************ initialise flexspi config ************************
flexspi_config_t config;
/*Get FLEXSPI default settings and configure the flexspi. */
FLEXSPI_GetDefaultConfig(&config);

/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableReadAddressOpt = true;
config.ahbConfig.enableAHBCachable = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad;
FLEXSPI_Init(FLEXSPI, &config);

#if 0

/* Configure flash settings according to serial flash feature. */
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortB1);

/* Update LUT table. */
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);

/* Do software reset. */
FLEXSPI_SoftwareReset(FLEXSPI);
#endif

}

[jay_heng]

You can link all your code into RAM (debug build in IDE) to test FlexSPI B1 port slave first. If it works well, then issue is caused by XIP build.

FlexSPI module has been initialize once to support code XIP, and then if you reconfigure FlexSPI via XIP code, you need to be careful. Don't destroy the FlexSPI configuration for XIP.

[Cindy]

Hi Jay_Heng,

I think I know the cause of the hardfault.
For my project, FLEXSPIA is connected to QSPI_NOR_FLASH (XIP) and FLEXSPIB is connected to FPGA.
FLEXSPIA is initialised before FLEXSPIB. I attempted to configure the clock(PFD0_FRAC, FLEXSPI_PODF, etc) differently for FLEXSPIB as I thought they have separate clock sources. I think this clock reconfiguration causes the hardfault.

However, please correctly if I am wrong.Please help to confirm that both FLEXSPIA and FLEXSPIB shares the common clock source.

Thank you.

Best Regards,
Cindy

[jay_heng · Accepted solution]

Yes, Port A and Port B from the same FlexSPI instance share the same clock source.