External Memory Interface Signals MIMXRT1176 SEMC

[muxeu]

Can you please tell me if I understand correctly that the external signals of the external memory interface SEMC_CSX0, SEMC_CSX1, SEMC_CSX2, SEMC_CSX3 refer to memory areas SEMC0, SEMC1, SEMC2, SEMC3 according to Table 3-1 from section 3.2 of the MIMXRT1170RM user manual?

[muxeu]

Clarifying questions:
Thanks for the answer. Perhaps I did not quite correctly formulate the question. I have already found these sections of the documentation, but they did not give me clarity.
1. What is the difference between SEMC_CS0 (E6 - GPIO_EMC_B1_29) and SEMC_CSX0 (L1 - GPIO_EMC_B1_41)? Why are each of them allocated separate external contacts?
2. The IOCR register indicates that for MUX_CSX0, MUX_CSX1, MUX_CSX2, MUX_CSX3 SDRAM CS1, 2, 3 options can be set, but there is no SDRAM CS0 option, why?
3. What is the difference between SDRAM CS1, SDRAM CS2, SDRAM CS3 options within MUX_CSX0, 1, 2, 3, if I configure the external SEMC_CSX3 signal through the MUX_CSX3 bit field, what will the setting of the SDRAM CS2 option mean?

[gusarambula · Accepted solution]

Hello Muxeu,

My apologies. Yes, the naming conventions may be a bit cumbersome.

The SEMC_CS0 is a fixed chip select for the SDRAM and the SEMC_CSX0 is part of the four available configurable chip selects for SDRAM/NAND/NOR/SRAM/DBI modes. This is a bit more clear in Table 29-6 of the i.MXRT1170 Reference Manual (Rev 1).

If you will use the SDRAM mode, you would use SEMC_CS0 for SDRAM CS0 and configure the IOCR register and use the SEMC_CSX signals for additional SDRAM CSx signals.

The different SDRAM CSx signals are tied to the available configurable SDRAM memory regions on the SEMC. When following section 29.6.1 of the SDRAM application sequence, you may see that the regions are configured on the Base Registers for the memory regions of the SDRAM.

I hope that this information helps!

Regards,
Gustavo

[muxeu]

Thanks for answers.
I ignored Table 29-8 Base Registers Information. There is indicated the binding of the chip select to the memory area.

[gusarambula]

Hello muxeu,

The SEMC regions are configured by the IOCR[MUX_CSX0] register to select which chip selects pins will be used.

You may find more information in section 29.6 of the i.MXRT1170 Reference Manual, which provides more information on how to manage different setups.

Regards,
Gustavo